]> rtime.felk.cvut.cz Git - hercules2020/nv-tegra/linux-4.4.git/commitdiff
mmc: tegra: add platform data to enable/disable periodic cache flush
authorR Raj Kumar <rrajk@nvidia.com>
Tue, 12 Jan 2016 07:07:24 +0000 (12:37 +0530)
committerR Raj Kumar <rrajk@nvidia.com>
Mon, 27 Jun 2016 06:22:09 +0000 (23:22 -0700)
Added platform data member for enabling/disabling
periodic cache flush support for eMMC device.
Parse periodic cache flush timeout value from dt.

Bug 200165213

Change-Id: I9e13637e20fadffb0183c4d089e167fa6c474f1a
Reviewed-on: http://git-master/r/931589

Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Change-Id: I15c6477ea5b5703b8801d1a746fc762ddf8c42d4
Reviewed-on: http://git-master/r/1171080
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
drivers/mmc/host/sdhci-tegra.c
include/linux/platform_data/mmc-sdhci-tegra.h

index 695ec6a0aae01e5175072f0592026a8862c4e939..735ef02892d548bb6afc4e688556570856cebd69 100644 (file)
@@ -1326,6 +1326,19 @@ static int sdhci_tegra_parse_dt(struct device *dev)
        plat->enable_hw_cq =
                of_property_read_bool(np, "nvidia,enable-hwcq");
 #endif
+       plat->en_periodic_cflush = of_property_read_bool(np,
+                       "nvidia,en-periodic-cflush");
+       if (plat->en_periodic_cflush) {
+               val = 0;
+               of_property_read_u32(np, "nvidia,periodic-cflush-to", &val);
+               host->mmc->flush_timeout = val;
+               if (val == 0) {
+                       plat->en_periodic_cflush = false;
+                       dev_warn(dev, "Periodic cache flush feature disabled,"
+                               "since flush timeout value is zero.\n");
+               }
+       }
+
        tegra_host->plat = plat;
        return mmc_of_parse(host->mmc);
 }
@@ -1478,6 +1491,9 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
        if (plat->en_strobe)
                host->mmc->caps2 |= MMC_CAP2_EN_STROBE;
 
+       if (plat->en_periodic_cflush)
+               host->mmc->caps2 |= MMC_CAP2_PERIODIC_CACHE_FLUSH;
+
 #ifdef CONFIG_MMC_CQ_HCI
        if (plat->enable_hw_cq) {
                host->mmc->caps2 |= MMC_CAP2_HW_CQ;
index c3ce08bf7bed97d9ab73b9ca396cf396021ad3ab..f0fcd7121973d9339955f7e7640e2cfd66e685a0 100644 (file)
@@ -52,6 +52,7 @@ struct tegra_sdhci_platform_data {
        unsigned int tap_delay;
        unsigned int trim_delay;
        bool enable_hw_cq;
+       bool en_periodic_cflush; /* Enable periodic cache flush for eMMC */
 };
 
 #endif