Add support of configuring pixel width for symmetric even/odd
ganged mode. The value can be configured by dt property
'nvidia,dsi-even-odd-pixel-width'.
If the panel's dsi-ganged-type is
'TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD' and does not have this
dt property, the pixel width is set to 1 by default.
Bug
1609219
Change-Id: I96205754875ea9f5c2e2a5c7f8e8034ef74240e2
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: http://git-master/r/733560
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
- nvidia,dsi-te-gpio: specifies a GPIO used for dsi panel TE signal.
- nvidia,nvidia,dsi-ganged-type: specifies dsi ganged type. 1 for TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT,
2 for TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD, 3 for TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP
+ - nvidia,dsi-even-odd-pixel-width: pixel width for symmetric even/odd split, max value is 0x1FFF.
- nvidia,dsi-phy-hsdexit: dsi phy timing, t_hsdexit_ns.
- nvidia,dsi-phy-hstrail: dsi phy timing, t_hstrail_ns.
- nvidia,dsi-phy-datzero: dsi phy timing, t_datzero_ns.