The tegra dfll clock uses regulator_list_voltage to setup the LUT during init
when blocking calls are not permitted. Therefor we need a
regulator_list_voltage_unlocked version.
Change-Id: I0a6ec5335c53618d4f964f7f258ae6301f414460
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/
1226164
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
}
EXPORT_SYMBOL_GPL(regulator_list_voltage);
+int regulator_list_voltage_unlocked(struct regulator *regulator,
+ unsigned selector)
+{
+ return _regulator_list_voltage(regulator, selector, 0);
+}
+EXPORT_SYMBOL_GPL(regulator_list_voltage_unlocked);
+
/**
* regulator_get_regmap - get the regulator's register map
* @regulator: regulator source
int regulator_can_change_voltage(struct regulator *regulator);
int regulator_count_voltages(struct regulator *regulator);
int regulator_list_voltage(struct regulator *regulator, unsigned selector);
+int regulator_list_voltage_unlocked(struct regulator *regulator,
+ unsigned selector);
int regulator_is_supported_voltage(struct regulator *regulator,
int min_uV, int max_uV);
unsigned int regulator_get_linear_step(struct regulator *regulator);
return -EINVAL;
}
+static inline int regulator_list_voltage_unlocked(struct regulator *regulator,
+ unsigned selector)
+{
+ return -EINVAL;
+}
+
#endif
static inline int regulator_set_voltage_triplet(struct regulator *regulator,