arm64: add setup function for cortex-a57

The L2CTLR_EL1 register is programmed here to set correct L2
data ram latency. If it's already 2, do not write to L2CTLR_EL1.

Change-Id: I628b1b1c3a6a419a24eabc22d1b254908b276490
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/348305
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

diff --git a/arch/arm64/kernel/cputable.c b/arch/arm64/kernel/cputable.c
index 54d0b85ffa51419b23394668e1d5893d061684dc..4c3c060dd8ae7bfe5c7edb198364a8cc726b7d43 100644 (file)
--- a/arch/arm64/kernel/cputable.c
+++ b/arch/arm64/kernel/cputable.c
@@ -20,6 +20,7 @@
 
 #include <asm/cputable.h>
 
+extern unsigned long __cortexa57_cpu_setup(void);
 extern unsigned long __cpu_setup(void);
 
 struct cpu_info cpu_table[] = {
@@ -29,6 +30,12 @@ struct cpu_info cpu_table[] = {
                .cpu_name       = "NVIDIA Denver 1.0",
                .cpu_setup      = __cpu_setup,
        },
+       {
+               .cpu_id_val     = 0x410fd070,
+               .cpu_id_mask    = 0xff0ffff0,
+               .cpu_name       = "Cortex A57 Processor",
+               .cpu_setup      = __cortexa57_cpu_setup,
+       },
        {
                .cpu_id_val     = 0x000f0000,
                .cpu_id_mask    = 0x000f0000,

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 4e778b13291b74edbdee72a713d899ab13dad54c..129e1a5043ae36134e494d1988644a5eb6a55b4f 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -243,6 +243,20 @@ ENTRY(__cpu_setup)
        ret                                     // return to head.S
 ENDPROC(__cpu_setup)
 
+ENTRY(__cortexa57_cpu_setup)
+
+       mrs     x0, s3_1_c11_c0_2
+       and     x1, x0, #7
+       cmp     x1, #2
+       b.eq    __cpu_setup
+       mov     x1, #7
+       bic     x0, x0, x1
+       orr     x0, x0, #2                      // set data RAM latency to 3
+       msr     s3_1_c11_c0_2, x0
+
+       b       __cpu_setup
+ENDPROC(__cortexa57_cpu_setup)
+
        /*
         *                 n n            T
         *       U E      WT T UD     US IHBS