platform: tegra: mc: allow modules to access mc registers

mc_readl needs mc, mc_channels and mc_regs to be available.
Instead of exporting all symbols or modifying the existing mc.h,
it is safer and simpler to add new tegra_mc_readl/writel and
use them in modules instead.

bug 200247850

Change-Id: I42cb1dffe4e0fc028e363c349ed6c7c6c922f98b
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/1260671
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>

diff --git a/drivers/platform/tegra/mc/mc.c b/drivers/platform/tegra/mc/mc.c
index 5ae23dea43c78fe228da9bf40371018a6af97a1e..ad28e210832c38d463ab683400a35e3a11056111 100644 (file)
--- a/drivers/platform/tegra/mc/mc.c
+++ b/drivers/platform/tegra/mc/mc.c
@@ -62,6 +62,18 @@ int mc_channels;
 void __iomem *mc;
 void __iomem *mc_regs[MC_MAX_CHANNELS];
 
+u32 tegra_mc_readl(u32 reg)
+{
+       return mc_readl(reg);
+}
+EXPORT_SYMBOL(tegra_mc_readl);
+
+void tegra_mc_writel(u32 val, u32 reg)
+{
+       mc_writel(val, reg);
+}
+EXPORT_SYMBOL(tegra_mc_writel);
+
 /*
  * Return carveout info for @co in @inf. If @nr is non-NULL then the number of
  * carveouts are also place in @*nr. If both @inf and @nr are NULL then the

diff --git a/include/linux/platform/tegra/mc.h b/include/linux/platform/tegra/mc.h
index 0d182420d214f1fe732b8e29e272c5ea2632c3d9..d18d8a26188352f484a74b19b581b14524f37f1f 100644 (file)
--- a/include/linux/platform/tegra/mc.h
+++ b/include/linux/platform/tegra/mc.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2010-2012 Google, Inc.
- * Copyright (C) 2013-2014, NVIDIA Corporation.  All rights reserved.
+ * Copyright (C) 2013-2016, NVIDIA Corporation.  All rights reserved.
  *
  * Author:
  *     Erik Gilling <konkers@google.com>
@@ -19,6 +19,7 @@
 #ifndef __MACH_TEGRA_MC_H
 #define __MACH_TEGRA_MC_H
 
+#include <linux/platform/tegra/tegra_mc.h>
 /* Pull in chip specific MC header - contains the regs for the platform. */
 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
 #include <linux/platform/tegra/mc-regs-t21x.h>
@@ -163,25 +164,6 @@ void         tegra21_mc_latency_allowance_save(u32 **pctx);
 void         tegra21_mc_latency_allowance_restore(u32 **pctx);
 #endif
 
-/*
- * API for reading carveout info.
- */
-enum carveout_desc {
-       MC_SECURITY_CARVEOUT1 = 0,
-       MC_SECURITY_CARVEOUT2,
-       MC_NR_CARVEOUTS
-};
-
-struct mc_carveout_info {
-       enum carveout_desc desc;
-
-       u64 base;
-       u64 size;
-};
-
-int mc_get_carveout_info(struct mc_carveout_info *inf, int *nr,
-                        enum carveout_desc co);
-
 /* API to get freqency switch latency at given MC freq.
  * freq_khz: Frequncy in KHz.
  * retruns latency in microseconds.

diff --git a/include/linux/platform/tegra/tegra_mc.h b/include/linux/platform/tegra/tegra_mc.h
new file mode 100644 (file)
index 0000000..5d5b071
--- /dev/null
+++ b/include/linux/platform/tegra/tegra_mc.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2016, NVIDIA Corporation.  All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __TEGRA_MC_H
+#define __TEGRA_MC_H
+
+/*
+ * API for reading carveout info.
+ */
+enum carveout_desc {
+       MC_SECURITY_CARVEOUT1 = 0,
+       MC_SECURITY_CARVEOUT2,
+       MC_NR_CARVEOUTS
+};
+
+struct mc_carveout_info {
+       enum carveout_desc desc;
+
+       u64 base;
+       u64 size;
+};
+
+#if defined(CONFIG_TEGRA_MC)
+
+/**
+ * Read from the MC.
+ *
+ * @idx The MC channel to read from.
+ * @reg The offset of the register to read.
+ *
+ * Read from the specified MC channel: 0 -> MC0, 1 -> MC1, etc. If @idx
+ * corresponds to a non-existent channel then 0 is returned.
+ */
+extern u32 tegra_mc_readl(u32 reg);
+
+/**
+ * Write to the MC.
+ *
+ * @idx The MC channel to write to.
+ * @val Value to write.
+ * @reg The offset of the register to write.
+ *
+ * Write to the specified MC channel: 0 -> MC0, 1 -> MC1, etc. For writes there
+ * is a special channel, %MC_BROADCAST_CHANNEL, which writes to all channels. If
+ * @idx corresponds to a non-existent channel then the write is dropped.
+ */
+extern void tegra_mc_writel(u32 val, u32 reg);
+
+extern int mc_get_carveout_info(struct mc_carveout_info *inf, int *nr,
+                        enum carveout_desc co);
+
+#else
+
+static inline u32 tegra_mc_readl(u32 reg)
+{
+       return 0xffffffff;
+}
+
+static inline void tegra_mc_writel(u32 val, u32 reg)
+{
+}
+
+static inline int mc_get_carveout_info(struct mc_carveout_info *inf, int *nr,
+                        enum carveout_desc co)
+{
+       return -ENODEV;
+}
+
+#endif
+
+#endif