driver: ahci: tegra: Update ahci_power_un_gate

For APBDEV_PMC_SATA_PWRGT_0:
     Set back PADPHY_IDDQ_SWCTL and PADPLL_IDDQ_SWCTL to 0.

For CLK_RST_CONTROLLER_SATA_PLL_CFG1
	Set back PADPLL_IDDQ2LANE_SLUMBER_DL to 3us.

Bug 1053727

Change-Id: I8718dc510823ee9fe1eb12c91459c128902b1212
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/225655
(cherry picked from commit a995a665f62301ac7ee71b4842a6d72f3b374e64)
Reviewed-on: http://git-master/r/248973
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Sumeet Gupta <sumeetg@nvidia.com>

diff --git a/drivers/ata/ahci-tegra.c b/drivers/ata/ahci-tegra.c
index 3c64cff4734ba2d24f1dc8ef51a7592cc9e617bc..49fce0035703b094bbb8361be582ca553c1fb96a 100644 (file)
--- a/drivers/ata/ahci-tegra.c
+++ b/drivers/ata/ahci-tegra.c
@@ -1537,18 +1537,24 @@ static bool tegra_ahci_power_un_gate(struct ata_host *host)
 
        tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
 
+       /* wait for SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY = 3 microseconds. */
+       val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
+       val &= ~IDDQ2LANE_SLUMBER_DLY_MASK;
+       val |= IDDQ2LANE_SLUMBER_DLY_3MS;
+       clk_writel(val, CLK_RST_SATA_PLL_CFG1_REG);
+
        /* get sata phy and pll out of iddq: */
        val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
-       val &= ~PADPLL_IDDQ_OVERRIDE_VALUE_MASK;
-       val |= PADPLL_IDDQ_OVERRIDE_VALUE_OFF;
+       val &= ~(PADPLL_IDDQ_OVERRIDE_VALUE_MASK | PADPLL_IDDQ_SWCTL_MASK);
+       val |= (PADPLL_IDDQ_SWCTL_OFF | PADPLL_IDDQ_OVERRIDE_VALUE_OFF);
        pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
        /* wait for delay of IDDQ2LAND_SLUMBER_DLY */
        val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
        dat = (val & IDDQ2LANE_SLUMBER_DLY_MASK) >> IDDQ2LANE_SLUMBER_DLY_SHIFT;
        udelay(dat);
        val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
-       val &= ~PADPHY_IDDQ_OVERRIDE_VALUE_MASK;
-       val |= PADPHY_IDDQ_OVERRIDE_VALUE_OFF;
+       val &= ~(PADPHY_IDDQ_OVERRIDE_VALUE_MASK | PADPHY_IDDQ_SWCTL_MASK);
+       val |= (PADPHY_IDDQ_SWCTL_OFF | PADPHY_IDDQ_OVERRIDE_VALUE_OFF);
        pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
 
        status = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_SATA);