The value derived and written to the PHY_CIL_COMMAND register is not
reliant on its current state (i.e. reading from and building on the
registers current value). Doing so can cause CSI issues when certain
timing conditions are met.
Removes dependency on PHY_CIL_COMMAND read and makes explicit NOP writes
for clarity.
Bug
200291915
Change-Id: I932b164c4ce065de9998800313f6982ddeaf2a76
Signed-off-by: Ian Kaszubski <ikaszubski@nvidia.com>
Reviewed-on: https://git-master/r/
1510765
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankit Gupta (SW-TEGRA) <ankitgu@nvidia.com>
Tested-by: Ankit Gupta (SW-TEGRA) <ankitgu@nvidia.com>
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
csi_write(chan,
TEGRA_CSI_CIL_OFFSET + TEGRA_CSI_CIL_PAD_CONFIG0, 0x0,
csi_port >> 1);
csi_write(chan,
TEGRA_CSI_CIL_OFFSET + TEGRA_CSI_CIL_PAD_CONFIG0, 0x0,
csi_port >> 1);
- val |= ((csi_port & 0x1) == PORT_A) ? CSI_A_PHY_CIL_ENABLE :
- CSI_B_PHY_CIL_ENABLE;
+ val = ((csi_port & 0x1) == PORT_A) ?
+ CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_NOP
+ : CSI_B_PHY_CIL_ENABLE | CSI_A_PHY_CIL_NOP;
csi_write(chan, TEGRA_CSI_PHY_CIL_COMMAND, val,
csi_port >> 1);
}
csi_write(chan, TEGRA_CSI_PHY_CIL_COMMAND, val,
csi_port >> 1);
}
if (chan->numlanes == 2) {
lanes |= CSIA << csi_port;
if (chan->numlanes == 2) {
lanes |= CSIA << csi_port;
- val = csi_read(chan, TEGRA_CSI_PHY_CIL_COMMAND,
- csi_port >> 1);
csi_write(chan,
TEGRA_CSI_CIL_OFFSET +
TEGRA_CSI_CIL_PAD_CONFIG0, 0x0, csi_port >> 1);
csi_write(chan,
TEGRA_CSI_CIL_OFFSET +
TEGRA_CSI_CIL_PAD_CONFIG0, 0x0, csi_port >> 1);
- val |= ((csi_port & 0x1) == PORT_A) ?
- CSI_A_PHY_CIL_ENABLE : CSI_B_PHY_CIL_ENABLE;
+ val = ((csi_port & 0x1) == PORT_A) ?
+ CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_NOP
+ : CSI_B_PHY_CIL_ENABLE | CSI_A_PHY_CIL_NOP;
csi_write(chan, TEGRA_CSI_PHY_CIL_COMMAND, val,
csi_port >> 1);
} else {
csi_write(chan, TEGRA_CSI_PHY_CIL_COMMAND, val,
csi_port >> 1);
} else {
*
* Tegra VI/CSI register offsets
*
*
* Tegra VI/CSI register offsets
*
- * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
/* CSI PHY registers */
/* CSI_PHY_CIL_COMMAND_0 offset 0x0d0 from TEGRA_CSI_PIXEL_PARSER_0_BASE */
#define TEGRA_CSI_PHY_CIL_COMMAND 0x0d0
/* CSI PHY registers */
/* CSI_PHY_CIL_COMMAND_0 offset 0x0d0 from TEGRA_CSI_PIXEL_PARSER_0_BASE */
#define TEGRA_CSI_PHY_CIL_COMMAND 0x0d0
+#define CSI_A_PHY_CIL_NOP 0x0
#define CSI_A_PHY_CIL_ENABLE 0x1
#define CSI_A_PHY_CIL_ENABLE 0x1
+#define CSI_B_PHY_CIL_NOP (0x0 << 8)
#define CSI_B_PHY_CIL_ENABLE (0x1 << 8)
/* CSI CIL registers: Starts from 0x92c, offset 0xF4 */
#define CSI_B_PHY_CIL_ENABLE (0x1 << 8)
/* CSI CIL registers: Starts from 0x92c, offset 0xF4 */