ASoC: tegra-alt: fix ahub clock rate

Currently we use 24Mhz for sampling rate less than 48Khz, So the ahub will
be runninng at 24MHz which is not enough to do SFC for 44.1 to 48Khz, So
change the code to use 49 MHz for ahub rate more than 11.025 KHz sampling
rates only.

Bug 200254129
Bug 1839027

Change-Id: Ia6a5b871aca29d8302cbeb8afb7c403065a62464
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Reviewed-on: http://git-master/r/1281088
Reviewed-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>

diff --git a/sound/soc/tegra-alt/tegra_asoc_utils_alt.c b/sound/soc/tegra-alt/tegra_asoc_utils_alt.c
index 209d87e80f5f8b87220d5a6442790a650e280867..3826a7b7a3d06f25bb7ead9d93e7eea8713d3a52 100644 (file)
--- a/sound/soc/tegra-alt/tegra_asoc_utils_alt.c
+++ b/sound/soc/tegra-alt/tegra_asoc_utils_alt.c
@@ -2,7 +2,7 @@
  * tegra_asoc_utils_alt.c - MCLK and DAP Utility driver
  *
  * Author: Stephen Warren <swarren@nvidia.com>
- * Copyright (c) 2010-2016 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2017 NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -178,11 +178,12 @@ int tegra_alt_asoc_utils_set_rate(struct tegra_asoc_audio_clock_info *data,
                        mclk = data->clk_rates[PLLA_OUT0_x11025_RATE];
                        ahub_rate = data->clk_rates[AHUB_x11025_RATE];
 
-                       if (srate <= 44100) {
+                       if (srate <= 11025) {
                                /* half the pll_a_out0 to support lower
                                 * sampling rate divider
                                 */
                                mclk = mclk >> 1;
+                               ahub_rate = ahub_rate >> 1;
                        }
                        /* aud_mclk should be 256*Fs */
                        clk_out_rate = srate << 8;
@@ -208,11 +209,12 @@ int tegra_alt_asoc_utils_set_rate(struct tegra_asoc_audio_clock_info *data,
                        mclk = data->clk_rates[PLLA_OUT0_x8000_RATE];
                        ahub_rate = data->clk_rates[AHUB_x8000_RATE];
 
-                       if (srate <= 48000) {
+                       if (srate <= 8000) {
                                /* half the pll_a_out0 to support lower
                                 * sampling rate divider
                                 */
                                mclk = mclk >> 1;
+                               ahub_rate = ahub_rate >> 1;
                        }
                        /* aud_mclk should be 256*Fs */
                        clk_out_rate = srate << 8;