ccflags-y += -I../nvhost/drivers/video/tegra/host
ccflags-y += -Idrivers/video/tegra/host
ccflags-y += -Idrivers/video/tegra/camera
+ccflags-y += -Idrivers/media/platform/tegra/vi
ccflags-y += -Werror
obj-y += camera_common.o mc_common.o core.o channel.o graph.o camera_gpio.o
#include <mach/io_dpd.h>
#include "mc_common.h"
+#include "vi.h"
-void tegra_channel_fmts_bitmap_init(struct tegra_channel *chan,
- struct tegra_vi_graph_entity *entity)
+void tegra_channel_write(struct tegra_channel *chan,
+ unsigned int addr, u32 val)
{
- int ret, index;
- struct v4l2_subdev *subdev = entity->subdev;
+ writel(val, chan->vi->iomem + addr);
+}
+
+/* CSI registers */
+static void csi_write(struct tegra_channel *chan, unsigned int addr, u32 val)
+{
+ writel(val, chan->csibase + addr);
+}
+
+static u32 csi_read(struct tegra_channel *chan, unsigned int addr)
+{
+ return readl(chan->csibase + addr);
+}
+
+static void tegra_channel_fmts_bitmap_init(struct tegra_channel *chan)
+{
+ int ret, index = 0, num_sd = 0;
+ struct v4l2_subdev *subdev = chan->subdev[0];
struct v4l2_subdev_mbus_code_enum code = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
bitmap_zero(chan->fmts_bitmap, MAX_FORMAT_NUM);
- while (1) {
+ while (subdev != NULL) {
ret = v4l2_subdev_call(subdev, pad, enum_mbus_code,
NULL, &code);
if (ret < 0)
bitmap_set(chan->fmts_bitmap, index, 1);
code.index++;
+ num_sd++;
+ subdev = chan->subdev[num_sd];
+ }
+
+ if (!num_sd) {
+ index = tegra_core_get_idx_by_code(TEGRA_VF_DEF);
+ if (index >= 0)
+ bitmap_set(chan->fmts_bitmap, index, 1);
}
if (bitmap_weight(chan->fmts_bitmap, MAX_FORMAT_NUM) == 0) {
}
}
-/* -----------------------------------------------------------------------------
- * videobuf2 queue operations
+/*
+ * -----------------------------------------------------------------------------
+ * Tegra channel frame setup and capture operations
+ * -----------------------------------------------------------------------------
*/
+static int tegra_channel_capture_setup(struct tegra_channel *chan)
+{
+ u32 height = chan->format.height;
+ u32 width = chan->format.width;
+ u32 format = chan->fmtinfo->img_fmt;
+ u32 data_type = chan->fmtinfo->img_dt;
+ u32 word_count = tegra_core_get_word_count(width, chan->fmtinfo);
+
+ csi_write(chan, TEGRA_VI_CSI_ERROR_STATUS, 0xFFFFFFFF);
+ csi_write(chan, TEGRA_VI_CSI_IMAGE_DEF,
+ ((chan->vi->pg_mode ? 0 : 1) << BYPASS_PXL_TRANSFORM_OFFSET) |
+ (format << IMAGE_DEF_FORMAT_OFFSET) |
+ IMAGE_DEF_DEST_MEM);
+ csi_write(chan, TEGRA_VI_CSI_IMAGE_DT, data_type);
+ csi_write(chan, TEGRA_VI_CSI_IMAGE_SIZE_WC, word_count);
+ csi_write(chan, TEGRA_VI_CSI_IMAGE_SIZE,
+ (height << IMAGE_SIZE_HEIGHT_OFFSET) | width);
+ return 0;
+}
+
+static void tegra_channel_capture_error(struct tegra_channel *chan)
+{
+ u32 val;
+
+ val = csi_read(chan, TEGRA_VI_CSI_ERROR_STATUS);
+ dev_err(&chan->video.dev, "TEGRA_VI_CSI_ERROR_STATUS 0x%08x\n", val);
+ tegra_csi_status(chan->vi->csi, chan->port);
+}
+
+static void tegra_channel_capture_frame(struct tegra_channel *chan,
+ struct tegra_channel_buffer *buf)
+{
+ int err = 0;
+ u32 thresh = 0, val, frame_start;
+ int bytes_per_line = chan->format.bytesperline;
+
+ /* Program buffer address by using surface 0 */
+ csi_write(chan, TEGRA_VI_CSI_SURFACE0_OFFSET_MSB, 0x0);
+ csi_write(chan, TEGRA_VI_CSI_SURFACE0_OFFSET_LSB, buf->addr);
+ csi_write(chan, TEGRA_VI_CSI_SURFACE0_STRIDE, bytes_per_line);
+
+ /* Program syncpoint */
+ thresh = nvhost_syncpt_incr_max_ext(chan->vi->ndev,
+ chan->syncpt, 1);
+ frame_start = VI_CSI_PP_FRAME_START(chan->port);
+ val = VI_CFG_VI_INCR_SYNCPT_COND(frame_start) | chan->syncpt;
+ tegra_channel_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, val);
+
+ csi_write(chan, TEGRA_VI_CSI_SINGLE_SHOT, SINGLE_SHOT_CAPTURE);
+
+ err = nvhost_syncpt_wait_timeout_ext(chan->vi->ndev,
+ chan->syncpt, thresh,
+ TEGRA_VI_SYNCPT_WAIT_TIMEOUT,
+ NULL,
+ NULL);
+ /* Move buffer to capture done queue */
+ spin_lock(&chan->done_lock);
+ list_add_tail(&buf->queue, &chan->done);
+ spin_unlock(&chan->done_lock);
+
+ /* Wait up kthread for capture done */
+ wake_up_interruptible(&chan->done_wait);
+
+ if (err) {
+ dev_err(&chan->video.dev, "frame start syncpt timeout!\n");
+ tegra_channel_capture_error(chan);
+ }
+}
+
+static void tegra_channel_capture_done(struct tegra_channel *chan,
+ struct tegra_channel_buffer *buf)
+{
+ struct vb2_v4l2_buffer *vb = &buf->buf;
+ int err = 0;
+ u32 thresh = 0, val, mw_ack_done;
+
+ /* Program syncpoint */
+ thresh = nvhost_syncpt_incr_max_ext(chan->vi->ndev,
+ chan->syncpt, 1);
+
+ mw_ack_done = VI_CSI_MW_ACK_DONE(chan->port);
+ val = VI_CFG_VI_INCR_SYNCPT_COND(mw_ack_done) | chan->syncpt;
+ tegra_channel_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, val);
+
+ err = nvhost_syncpt_wait_timeout_ext(chan->vi->ndev,
+ chan->syncpt, thresh,
+ TEGRA_VI_SYNCPT_WAIT_TIMEOUT,
+ NULL,
+ NULL);
+ if (err)
+ dev_err(&chan->video.dev, "MW_ACK_DONE syncpoint time out!\n");
+
+ /* Captured one frame */
+ vb->sequence = chan->sequence++;
+ vb->field = V4L2_FIELD_NONE;
+ v4l2_get_timestamp(&vb->timestamp);
+ vb2_set_plane_payload(&vb->vb2_buf, 0, chan->format.sizeimage);
+ vb2_buffer_done(&vb->vb2_buf, err < 0 ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
+}
+
+static int tegra_channel_kthread_capture_start(void *data)
+{
+ struct tegra_channel *chan = data;
+ struct tegra_channel_buffer *buf;
+
+ set_freezable();
+
+ while (1) {
+ try_to_freeze();
+ wait_event_interruptible(chan->start_wait,
+ !list_empty(&chan->capture) ||
+ kthread_should_stop());
+ if (kthread_should_stop())
+ break;
+
+ spin_lock(&chan->start_lock);
+ if (list_empty(&chan->capture)) {
+ spin_unlock(&chan->start_lock);
+ continue;
+ }
+
+ buf = list_entry(chan->capture.next,
+ struct tegra_channel_buffer, queue);
+ list_del_init(&buf->queue);
+ spin_unlock(&chan->start_lock);
+
+ tegra_channel_capture_frame(chan, buf);
+ }
+
+ return 0;
+}
+
+static int tegra_channel_kthread_capture_done(void *data)
+{
+ struct tegra_channel *chan = data;
+ struct tegra_channel_buffer *buf;
+
+ set_freezable();
+
+ while (1) {
+ try_to_freeze();
+ wait_event_interruptible(chan->done_wait,
+ !list_empty(&chan->done) ||
+ kthread_should_stop());
+ if (kthread_should_stop() && list_empty(&chan->done))
+ break;
+
+ spin_lock(&chan->done_lock);
+ if (list_empty(&chan->done)) {
+ spin_unlock(&chan->done_lock);
+ continue;
+ }
+
+ buf = list_entry(chan->done.next,
+ struct tegra_channel_buffer, queue);
+ list_del_init(&buf->queue);
+ spin_unlock(&chan->done_lock);
+
+ tegra_channel_capture_done(chan, buf);
+ }
+
+ return 0;
+}
+
+/*
+ * -----------------------------------------------------------------------------
+ * videobuf2 queue operations
+ * -----------------------------------------------------------------------------
+ */
static int
tegra_channel_queue_setup(struct vb2_queue *vq, const void *parg,
unsigned int *nbuffers, unsigned int *nplanes,
static int tegra_channel_buffer_prepare(struct vb2_buffer *vb)
{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct tegra_channel *chan = vb2_get_drv_priv(vb->vb2_queue);
- struct tegra_channel_buffer *buf = to_tegra_channel_buffer(vb);
+ struct tegra_channel_buffer *buf = to_tegra_channel_buffer(vbuf);
buf->chan = chan;
vb2_set_plane_payload(vb, 0, chan->format.sizeimage);
static void tegra_channel_buffer_queue(struct vb2_buffer *vb)
{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct tegra_channel *chan = vb2_get_drv_priv(vb->vb2_queue);
+ struct tegra_channel_buffer *buf = to_tegra_channel_buffer(vbuf);
+
/* for bypass mode - do nothing */
+ if (chan->bypass)
+ return;
+
+ /* Put buffer into the capture queue */
+ spin_lock(&chan->start_lock);
+ list_add_tail(&buf->queue, &chan->capture);
+ spin_unlock(&chan->start_lock);
+
+ /* Wait up kthread for capture */
+ wake_up_interruptible(&chan->start_wait);
+}
+
+/* Return all queued buffers back to videobuf2 */
+static void tegra_channel_queued_buf_done(struct tegra_channel *chan,
+ enum vb2_buffer_state state)
+{
+ struct tegra_channel_buffer *buf, *nbuf;
+
+ spin_lock(&chan->start_lock);
+ list_for_each_entry_safe(buf, nbuf, &chan->capture, queue) {
+ vb2_buffer_done(&buf->buf.vb2_buf, state);
+ list_del(&buf->queue);
+ }
+ spin_unlock(&chan->start_lock);
}
+/*
+ * -----------------------------------------------------------------------------
+ * subdevice set/unset operations
+ * -----------------------------------------------------------------------------
+ */
static int tegra_channel_set_stream(struct tegra_channel *chan, bool on)
{
int num_sd = 0;
if (ret < 0)
goto error_pipeline_start;
- /* Start the pipeline. */
- ret = tegra_channel_set_stream(chan, true);
+ if (!chan->vi->pg_mode) {
+ /* Start the pipeline. */
+ ret = tegra_channel_set_stream(chan, true);
+ if (ret < 0)
+ goto error_set_stream;
+ }
+
+ if (chan->bypass)
+ return ret;
+
+ tegra_csi_start_streaming(chan->vi->csi, chan->port);
+ /* Note: Program VI registers after TPG, sensors and CSI streaming */
+ ret = tegra_channel_capture_setup(chan);
if (ret < 0)
- goto error_set_stream;
+ goto error_capture_setup;
+
+ chan->sequence = 0;
+ /* Start kthread to capture data to buffer */
+ chan->kthread_capture_start = kthread_run(
+ tegra_channel_kthread_capture_start,
+ chan, chan->video.name);
+ if (IS_ERR(chan->kthread_capture_start)) {
+ dev_err(&chan->video.dev,
+ "failed to run kthread for capture start\n");
+ ret = PTR_ERR(chan->kthread_capture_start);
+ goto error_capture_setup;
+ }
+
+ chan->kthread_capture_done = kthread_run(
+ tegra_channel_kthread_capture_done,
+ chan, chan->video.name);
+ if (IS_ERR(chan->kthread_capture_done)) {
+ dev_err(&chan->video.dev,
+ "failed to run kthread for capture done\n");
+ ret = PTR_ERR(chan->kthread_capture_done);
+ goto error_capture_setup;
+ }
return 0;
+
+error_capture_setup:
+ tegra_channel_set_stream(chan, false);
error_set_stream:
media_entity_pipeline_stop(&chan->video.entity);
error_pipeline_start:
vq->start_streaming_called = 0;
+ tegra_channel_queued_buf_done(chan, VB2_BUF_STATE_QUEUED);
return ret;
}
{
struct tegra_channel *chan = vb2_get_drv_priv(vq);
- media_entity_pipeline_stop(&chan->video.entity);
+ if (!chan->bypass) {
+ /* Stop the kthread for capture */
+ kthread_stop(chan->kthread_capture_start);
+ chan->kthread_capture_start = NULL;
+ kthread_stop(chan->kthread_capture_done);
+ chan->kthread_capture_done = NULL;
+ }
- tegra_channel_set_stream(chan, false);
+ if (!chan->vi->pg_mode)
+ tegra_channel_set_stream(chan, false);
+
+ if (!chan->bypass) {
+ tegra_csi_stop_streaming(chan->vi->csi, chan->port);
+ tegra_channel_queued_buf_done(chan, VB2_BUF_STATE_ERROR);
+ }
+
+ media_entity_pipeline_stop(&chan->video.entity);
}
static const struct vb2_ops tegra_channel_queue_qops = {
if (ret < 0)
dev_err(chan->vi->dev,
"Channel controls setup failed\n");
+
+ tegra_channel_fmts_bitmap_init(chan);
}
- /* power on sensors connected in channel */
- ret = tegra_channel_set_power(chan, 1);
- if (ret < 0)
- return ret;
+ if (!chan->bypass) {
+ tegra_vi_power_on(chan);
+ tegra_csi_power(chan->vi->csi, chan->port, 1);
+ }
+
+ if (!chan->vi->pg_mode) {
+ /* power on sensors connected in channel */
+ ret = tegra_channel_set_power(chan, 1);
+ if (ret < 0)
+ return ret;
+ }
+
+ chan->saved_ctx_bypass = chan->bypass;
+ chan->saved_ctx_pgmode = chan->vi->pg_mode;
return v4l2_fh_open(fp);
}
struct video_device *vdev = video_devdata(fp);
struct tegra_channel *chan = video_get_drvdata(vdev);
- /* power off sensors connected in channel */
- ret = tegra_channel_set_power(chan, 0);
- if (ret < 0)
- dev_err(chan->vi->dev, "Failed to power off subdevices\n");
+ ret = vb2_fop_release(fp);
- return vb2_fop_release(fp);
+ if (!chan->saved_ctx_pgmode) {
+ /* power off sensors connected in channel */
+ ret = tegra_channel_set_power(chan, 0);
+ if (ret < 0)
+ dev_err(chan->vi->dev,
+ "Failed to power off subdevices\n");
+ }
+
+ if (!chan->saved_ctx_bypass) {
+ int pg_mode = chan->vi->csi->pg_mode;
+ /* save TPG mode context for clean closure of CSI */
+ chan->vi->csi->pg_mode = chan->saved_ctx_pgmode;
+ tegra_csi_power(chan->vi->csi, chan->port, 0);
+ chan->vi->csi->pg_mode = pg_mode;
+ tegra_vi_power_off(chan->vi);
+ }
+
+ return ret;
}
/* -----------------------------------------------------------------------------
.mmap = vb2_fop_mmap,
};
-static int tegra_channel_init(struct tegra_mc_vi *vi, unsigned int port)
+static void vi_channel_syncpt_init(struct tegra_channel *chan)
+{
+ chan->syncpt = nvhost_get_syncpt_client_managed(chan->vi->ndev, "vi");
+}
+
+static void vi_channel_syncpt_free(struct tegra_channel *chan)
+{
+ nvhost_syncpt_put_ref_ext(chan->vi->ndev, chan->syncpt);
+}
+
+static int tegra_channel_init(struct tegra_mc_vi *vi, unsigned int index)
{
int ret;
- struct tegra_channel *chan = &vi->chans[port];
+ struct tegra_channel *chan = &vi->chans[index];
chan->vi = vi;
- chan->port = port;
+ tegra_vi_get_port_info(chan, vi->dev->of_node, index);
+ if (csi_port_is_valid(chan->port)) {
+ chan->csibase = vi->iomem + TEGRA_VI_CSI_BASE(chan->port);
+ set_csi_portinfo(vi->csi, chan->port, chan->numlanes);
+ }
chan->align = 64;
chan->num_subdevs = 0;
+ mutex_init(&chan->video_lock);
+ INIT_LIST_HEAD(&chan->capture);
+ INIT_LIST_HEAD(&chan->done);
+ init_waitqueue_head(&chan->start_wait);
+ init_waitqueue_head(&chan->done_wait);
+ spin_lock_init(&chan->start_lock);
+ spin_lock_init(&chan->done_lock);
/* Init video format */
chan->fmtinfo = tegra_core_get_format_by_code(TEGRA_VF_DEF);
chan->video.v4l2_dev = &vi->v4l2_dev;
chan->video.queue = &chan->queue;
snprintf(chan->video.name, sizeof(chan->video.name), "%s-%s-%u",
- dev_name(vi->dev), "output", port);
+ dev_name(vi->dev), "output", chan->port);
chan->video.vfl_type = VFL_TYPE_GRABBER;
chan->video.vfl_dir = VFL_DIR_RX;
chan->video.release = video_device_release_empty;
chan->video.ioctl_ops = &tegra_channel_ioctl_ops;
chan->video.ctrl_handler = &chan->ctrl_handler;
+ chan->video.lock = &chan->video_lock;
video_set_drvdata(&chan->video, chan);
#if defined(CONFIG_VIDEOBUF2_DMA_CONTIG)
+ vi_channel_syncpt_init(chan);
+
/* get the buffers queue... */
- chan->alloc_ctx = vb2_dma_contig_init_ctx(&chan->video.dev);
+ chan->alloc_ctx = vb2_dma_contig_init_ctx(chan->vi->dev);
if (IS_ERR(chan->alloc_ctx)) {
dev_err(chan->vi->dev, "failed to init vb2 buffer\n");
ret = -ENOMEM;
chan->queue.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
chan->queue.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ | VB2_USERPTR;
+ chan->queue.lock = &chan->video_lock;
chan->queue.drv_priv = chan;
chan->queue.buf_struct_size = sizeof(struct tegra_channel_buffer);
chan->queue.ops = &tegra_channel_queue_qops;
vb2_dma_contig_cleanup_ctx(chan->alloc_ctx);
#endif
+ vi_channel_syncpt_free(chan);
media_entity_cleanup(&chan->video.entity);
return 0;
sink->name, sink_pad->index);
break;
}
-
- tegra_channel_fmts_bitmap_init(chan, ent);
} while (next != NULL);
of_node_put(ep);
}
}
+int tegra_vi_get_port_info(struct tegra_channel *chan,
+ struct device_node *node, unsigned int index)
+{
+ struct device_node *ep = NULL;
+ struct device_node *ports;
+ struct device_node *port;
+ int value = 0xFFFF;
+ int ret = 0;
+
+ ports = of_get_child_by_name(node, "ports");
+ if (ports == NULL)
+ ports = node;
+
+ for_each_child_of_node(ports, port) {
+ if (!port->name || of_node_cmp(port->name, "port"))
+ continue;
+
+ ret = of_property_read_u32(port, "reg", &value);
+ if (ret < 0)
+ continue;
+
+ if (value != index)
+ continue;
+
+ for_each_child_of_node(port, ep) {
+ if (!ep->name || of_node_cmp(ep->name, "endpoint"))
+ continue;
+
+ /* Get CSI port */
+ ret = of_property_read_u32(ep, "csi-port", &value);
+ if (ret < 0)
+ pr_info("csi port error\n");
+ chan->port = value;
+
+ /* Get number of data lanes for the endpoint */
+ ret = of_property_read_u32(ep, "bus-width", &value);
+ if (ret < 0)
+ pr_info("num of lanes error\n");
+ chan->numlanes = value;
+
+ }
+ }
+
+ return ret;
+}
static int tegra_vi_graph_parse_one(struct tegra_mc_vi *vi,
struct device_node *node)
#include "dev.h"
#include "mc_common.h"
+#include "vi.h"
+#include "registers.h"
#define TPG_CHANNELS 6
#define INVALID_PORT 100
+/* In TPG mode, VI only support 2 formats */
+static void vi_tpg_fmts_bitmap_init(struct tegra_mc_vi *vi)
+{
+ int index;
+
+ bitmap_zero(vi->tpg_fmts_bitmap, MAX_FORMAT_NUM);
+
+ index = tegra_core_get_idx_by_code(MEDIA_BUS_FMT_SRGGB10_1X10);
+ bitmap_set(vi->tpg_fmts_bitmap, index, 1);
+
+ index = tegra_core_get_idx_by_code(MEDIA_BUS_FMT_RGB888_1X32_PADHI);
+ bitmap_set(vi->tpg_fmts_bitmap, index, 1);
+}
+
+int tegra_vi_power_on(struct tegra_channel *chan)
+{
+ int ret;
+ struct tegra_mc_vi *vi = chan->vi;
+
+ ret = nvhost_module_busy_ext(vi->ndev);
+ if (ret) {
+ dev_err(vi->dev, "%s:nvhost module is busy\n", __func__);
+ return ret;
+ }
+
+ if (vi->reg) {
+ ret = regulator_enable(vi->reg);
+ if (ret) {
+ dev_err(vi->dev, "%s: enable csi regulator failed.\n",
+ __func__);
+ goto error_regulator_fail;
+ }
+ }
+
+ tegra_channel_write(chan, TEGRA_VI_CFG_CG_CTRL, 1);
+
+ /* unpowergate VE */
+ ret = tegra_unpowergate_partition(TEGRA_POWERGATE_VENC);
+ if (ret) {
+ dev_err(vi->dev, "failed to unpower gate VI\n");
+ goto error_unpowergate;
+ }
+
+ /* clock settings */
+ clk_prepare_enable(vi->clk);
+ ret = clk_set_rate(vi->clk, 408000000);
+ if (ret) {
+ dev_err(vi->dev, "failed to set vi clock to 408MHz!\n");
+ goto error_clk_set_rate;
+ }
+
+ return 0;
+
+error_clk_set_rate:
+ tegra_powergate_partition(TEGRA_POWERGATE_VENC);
+error_unpowergate:
+ regulator_disable(vi->reg);
+error_regulator_fail:
+ nvhost_module_idle_ext(vi->ndev);
+
+ return ret;
+}
+
+void tegra_vi_power_off(struct tegra_mc_vi *vi)
+{
+ clk_disable_unprepare(vi->clk);
+ tegra_powergate_partition(TEGRA_POWERGATE_VENC);
+ regulator_disable(vi->reg);
+ nvhost_module_idle_ext(vi->ndev);
+}
+
/* -----------------------------------------------------------------------------
* Media Controller and V4L2
*/
dev_info(&vi->ndev->dev, "Turning on TPG mode\n");
}
vi->pg_mode = ctrl->val;
+ vi->csi->pg_mode = vi->pg_mode;
break;
case V4L2_CID_VI_SET_BYPASS_PORT:
- if (vi->pg_mode) {
- dev_info(&vi->ndev->dev, "Turn off TPG mode\n");
- set_v4l2_ctrl(vi->pattern, 0);
- vi->pg_mode = 0;
- }
-
if (ctrl->val < vi->num_channels) {
chan = &vi->chans[ctrl->val];
chan->bypass = 1;
+ if (vi->pg_mode) {
+ dev_info(&vi->ndev->dev,
+ "Turning off TPG mode\n");
+ set_v4l2_ctrl(vi->pattern, 0);
+ vi->pg_mode = vi->csi->pg_mode = 0;
+ }
} else
/* set all channels to vi mode for invalid port */
set_vi_mode(vi);
int ret;
vi->pg_mode = 0;
+ vi_tpg_fmts_bitmap_init(vi);
+
vi->media_dev.dev = vi->dev;
strlcpy(vi->media_dev.model, "NVIDIA Tegra Video Input Device",
sizeof(vi->media_dev.model));
return ret;
}
+static int vi_get_clks(struct tegra_mc_vi *vi, struct platform_device *pdev)
+{
+ int ret = 0;
+
+ vi->clk = devm_clk_get(&pdev->dev, "vi");
+ if (IS_ERR(vi->clk)) {
+ dev_err(&pdev->dev, "Failed to get vi clock\n");
+ return PTR_ERR(vi->clk);
+ }
+
+ return ret;
+}
+
static int vi_parse_dt(struct tegra_mc_vi *vi, struct platform_device *dev)
{
int err = 0;
return 0;
}
+static void set_vi_register_base(struct tegra_mc_vi *mc_vi,
+ void __iomem *regbase)
+{
+ mc_vi->iomem = regbase;
+}
+
int tegra_vi_media_controller_init(struct tegra_mc_vi *mc_vi,
struct platform_device *pdev)
{
int err = 0;
+ struct nvhost_device_data *pdata = pdev->dev.platform_data;
+
+ set_vi_register_base(mc_vi, pdata->aperture[0]);
+
+ err = vi_get_clks(mc_vi, pdev);
+ if (err)
+ return err;
err = vi_parse_dt(mc_vi, pdev);
if (err)
#include <media/v4l2-device.h>
#include <media/v4l2-dev.h>
#include <media/videobuf2-core.h>
-#include <media/mc_common.h>
#include "core.h"
+#include "../csi/csi.h"
#define MAX_FORMAT_NUM 64
#define MAX_SUBDEVICES 4
* @addr: Tegra IOVA buffer address for VI output
*/
struct tegra_channel_buffer {
- struct vb2_buffer buf;
+ struct vb2_v4l2_buffer buf;
struct list_head queue;
struct tegra_channel *chan;
struct video_device video;
struct media_pad pad;
struct media_pipeline pipe;
+ struct mutex video_lock;
struct tegra_mc_vi *vi;
struct v4l2_subdev *subdev[MAX_SUBDEVICES];
struct v4l2_pix_format format;
const struct tegra_video_format *fmtinfo;
+ unsigned int syncpt;
+
+ struct task_struct *kthread_capture_start;
+ wait_queue_head_t start_wait;
+ struct task_struct *kthread_capture_done;
+ wait_queue_head_t done_wait;
struct vb2_queue queue;
void *alloc_ctx;
+ struct list_head capture;
+ spinlock_t start_lock;
+ struct list_head done;
+ spinlock_t done_lock;
- void __iomem *csi;
+ void __iomem *csibase;
unsigned int align;
unsigned int port;
+ unsigned int numlanes;
unsigned int io_id;
unsigned int num_subdevs;
+ unsigned int sequence;
+ unsigned int saved_ctx_bypass;
+ unsigned int saved_ctx_pgmode;
DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM);
bool bypass;
struct device *dev;
struct nvhost_device_data *ndata;
+ struct regulator *reg;
+ struct clk *clk;
+ struct clk *parent_clk;
+
struct v4l2_async_notifier notifier;
struct list_head entities;
unsigned int num_channels;
unsigned int num_subdevs;
+ struct tegra_csi_device *csi;
struct tegra_channel *chans;
+ void __iomem *iomem;
struct v4l2_ctrl_handler ctrl_handler;
struct v4l2_ctrl *pattern;
bool has_sensors;
};
+int tegra_vi_get_port_info(struct tegra_channel *chan,
+ struct device_node *node, unsigned int index);
+void tegra_channel_write(struct tegra_channel *chan,
+ unsigned int addr, u32 val);
void tegra_vi_v4l2_cleanup(struct tegra_mc_vi *vi);
int tegra_vi_v4l2_init(struct tegra_mc_vi *vi);
int tegra_vi_graph_init(struct tegra_mc_vi *vi);
void tegra_vi_graph_cleanup(struct tegra_mc_vi *vi);
int tegra_vi_channels_init(struct tegra_mc_vi *vi);
int tegra_vi_channels_cleanup(struct tegra_mc_vi *vi);
-void tegra_channel_fmts_bitmap_init(struct tegra_channel *chan,
- struct tegra_vi_graph_entity *entity);
+int tegra_vi_power_on(struct tegra_channel *chan);
+void tegra_vi_power_off(struct tegra_mc_vi *vi);
int tegra_vi_media_controller_init(struct tegra_mc_vi *mc_vi,
struct platform_device *pdev);
void tegra_vi_media_controller_cleanup(struct tegra_mc_vi *mc_vi);
--- /dev/null
+/*
+ * drivers/media/platform/tegra/camera/registers.h
+ *
+ * Tegra VI/CSI register offsets
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __REGISTERS_H__
+#define __REGISTERS_H__
+
+/* VI registers */
+#define TEGRA_VI_SYNCPT_WAIT_TIMEOUT 200
+#define TEGRA_VI_CFG_VI_INCR_SYNCPT 0x000
+#define VI_CFG_VI_INCR_SYNCPT_COND(x) (x << 8)
+#define VI_CSI_PP_LINE_START(port) (4 + (port) * 4)
+#define VI_CSI_PP_FRAME_START(port) (5 + (port) * 4)
+#define VI_CSI_MW_REQ_DONE(port) (6 + (port) * 4)
+#define VI_CSI_MW_ACK_DONE(port) (7 + (port) * 4)
+
+#define TEGRA_VI_CFG_VI_INCR_SYNCPT_CNTRL 0x004
+#define TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR 0x008
+#define TEGRA_VI_CFG_CTXSW 0x020
+#define TEGRA_VI_CFG_INTSTATUS 0x024
+#define TEGRA_VI_CFG_PWM_CONTROL 0x038
+#define TEGRA_VI_CFG_PWM_HIGH_PULSE 0x03c
+#define TEGRA_VI_CFG_PWM_LOW_PULSE 0x040
+#define TEGRA_VI_CFG_PWM_SELECT_PULSE_A 0x044
+#define TEGRA_VI_CFG_PWM_SELECT_PULSE_B 0x048
+#define TEGRA_VI_CFG_PWM_SELECT_PULSE_C 0x04c
+#define TEGRA_VI_CFG_PWM_SELECT_PULSE_D 0x050
+#define TEGRA_VI_CFG_VGP1 0x064
+#define TEGRA_VI_CFG_VGP2 0x068
+#define TEGRA_VI_CFG_VGP3 0x06c
+#define TEGRA_VI_CFG_VGP4 0x070
+#define TEGRA_VI_CFG_VGP5 0x074
+#define TEGRA_VI_CFG_VGP6 0x078
+#define TEGRA_VI_CFG_INTERRUPT_MASK 0x08c
+#define TEGRA_VI_CFG_INTERRUPT_TYPE_SELECT 0x090
+#define TEGRA_VI_CFG_INTERRUPT_POLARITY_SELECT 0x094
+#define TEGRA_VI_CFG_INTERRUPT_STATUS 0x098
+#define TEGRA_VI_CFG_VGP_SYNCPT_CONFIG 0x0ac
+#define TEGRA_VI_CFG_VI_SW_RESET 0x0b4
+#define TEGRA_VI_CFG_CG_CTRL 0x0b8
+#define VI_CG_2ND_LEVEL_EN 0x1
+#define TEGRA_VI_CFG_VI_MCCIF_FIFOCTRL 0x0e4
+#define TEGRA_VI_CFG_TIMEOUT_WCOAL_VI 0x0e8
+#define TEGRA_VI_CFG_DVFS 0x0f0
+#define TEGRA_VI_CFG_RESERVE 0x0f4
+#define TEGRA_VI_CFG_RESERVE_1 0x0f8
+
+/* CSI registers */
+#define TEGRA_VI_CSI_BASE(x) (0x100 + (x) * 0x100)
+
+#define TEGRA_VI_CSI_SW_RESET 0x000
+#define TEGRA_VI_CSI_SINGLE_SHOT 0x004
+#define SINGLE_SHOT_CAPTURE 0x1
+#define TEGRA_VI_CSI_SINGLE_SHOT_STATE_UPDATE 0x008
+#define TEGRA_VI_CSI_IMAGE_DEF 0x00c
+#define BYPASS_PXL_TRANSFORM_OFFSET 24
+#define IMAGE_DEF_FORMAT_OFFSET 16
+#define IMAGE_DEF_DEST_MEM 0x1
+#define TEGRA_VI_CSI_RGB2Y_CTRL 0x010
+#define TEGRA_VI_CSI_MEM_TILING 0x014
+#define TEGRA_VI_CSI_IMAGE_SIZE 0x018
+#define IMAGE_SIZE_HEIGHT_OFFSET 16
+#define TEGRA_VI_CSI_IMAGE_SIZE_WC 0x01c
+#define TEGRA_VI_CSI_IMAGE_DT 0x020
+#define TEGRA_VI_CSI_SURFACE0_OFFSET_MSB 0x024
+#define TEGRA_VI_CSI_SURFACE0_OFFSET_LSB 0x028
+#define TEGRA_VI_CSI_SURFACE1_OFFSET_MSB 0x02c
+#define TEGRA_VI_CSI_SURFACE1_OFFSET_LSB 0x030
+#define TEGRA_VI_CSI_SURFACE2_OFFSET_MSB 0x034
+#define TEGRA_VI_CSI_SURFACE2_OFFSET_LSB 0x038
+#define TEGRA_VI_CSI_SURFACE0_BF_OFFSET_MSB 0x03c
+#define TEGRA_VI_CSI_SURFACE0_BF_OFFSET_LSB 0x040
+#define TEGRA_VI_CSI_SURFACE1_BF_OFFSET_MSB 0x044
+#define TEGRA_VI_CSI_SURFACE1_BF_OFFSET_LSB 0x048
+#define TEGRA_VI_CSI_SURFACE2_BF_OFFSET_MSB 0x04c
+#define TEGRA_VI_CSI_SURFACE2_BF_OFFSET_LSB 0x050
+#define TEGRA_VI_CSI_SURFACE0_STRIDE 0x054
+#define TEGRA_VI_CSI_SURFACE1_STRIDE 0x058
+#define TEGRA_VI_CSI_SURFACE2_STRIDE 0x05c
+#define TEGRA_VI_CSI_SURFACE_HEIGHT0 0x060
+#define TEGRA_VI_CSI_ISPINTF_CONFIG 0x064
+#define TEGRA_VI_CSI_ERROR_STATUS 0x084
+#define TEGRA_VI_CSI_ERROR_INT_MASK 0x088
+#define TEGRA_VI_CSI_WD_CTRL 0x08c
+#define TEGRA_VI_CSI_WD_PERIOD 0x090
+
+/* CSI Pixel Parser registers: Starts from 0x838, offset 0x0 */
+#define TEGRA_CSI_INPUT_STREAM_CONTROL 0x000
+#define CSI_SKIP_PACKET_THRESHOLD_OFFSET 16
+
+#define TEGRA_CSI_PIXEL_STREAM_CONTROL0 0x004
+#define CSI_PP_PACKET_HEADER_SENT (0x1 << 4)
+#define CSI_PP_DATA_IDENTIFIER_ENABLE (0x1 << 5)
+#define CSI_PP_WORD_COUNT_SELECT_HEADER (0x1 << 6)
+#define CSI_PP_CRC_CHECK_ENABLE (0x1 << 7)
+#define CSI_PP_WC_CHECK (0x1 << 8)
+#define CSI_PP_OUTPUT_FORMAT_STORE (0x3 << 16)
+#define CSI_PP_HEADER_EC_DISABLE (0x1 << 27)
+#define CSI_PPA_PAD_FRAME_NOPAD (0x2 << 28)
+
+#define TEGRA_CSI_PIXEL_STREAM_CONTROL1 0x008
+#define CSI_PP_TOP_FIELD_FRAME_OFFSET 0
+#define CSI_PP_TOP_FIELD_FRAME_MASK_OFFSET 4
+
+#define TEGRA_CSI_PIXEL_STREAM_GAP 0x00c
+#define PP_FRAME_MIN_GAP_OFFSET 16
+
+#define TEGRA_CSI_PIXEL_STREAM_PP_COMMAND 0x010
+#define CSI_PP_ENABLE 0x1
+#define CSI_PP_DISABLE 0x2
+#define CSI_PP_RST 0x3
+#define CSI_PP_SINGLE_SHOT_ENABLE (0x1 << 2)
+#define CSI_PP_START_MARKER_FRAME_MAX_OFFSET 12
+
+#define TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME 0x014
+#define TEGRA_CSI_PIXEL_PARSER_INTERRUPT_MASK 0x018
+#define TEGRA_CSI_PIXEL_PARSER_STATUS 0x01c
+#define TEGRA_CSI_CSI_SW_SENSOR_RESET 0x020
+
+/* CSI PHY registers */
+#define TEGRA_CSI_PHY_CIL_COMMAND 0x0d0
+#define CSI_A_PHY_CIL_ENABLE 0x1
+#define CSI_B_PHY_CIL_ENABLE (0x1 << 8)
+
+/* CSI CIL registers: Starts from 0x92c, offset 0xF4 */
+#define TEGRA_CSI_CIL_OFFSET 0x0f4
+
+#define TEGRA_CSI_CIL_PAD_CONFIG0 0x000
+#define BRICK_CLOCK_A_4X (0x1 << 16)
+#define BRICK_CLOCK_B_4X (0x2 << 16)
+#define TEGRA_CSI_CIL_PAD_CONFIG1 0x004
+#define TEGRA_CSI_CIL_PHY_CONTROL 0x008
+#define TEGRA_CSI_CIL_INTERRUPT_MASK 0x00c
+#define TEGRA_CSI_CIL_STATUS 0x010
+#define TEGRA_CSI_CILX_STATUS 0x014
+#define TEGRA_CSI_CIL_ESCAPE_MODE_COMMAND 0x018
+#define TEGRA_CSI_CIL_ESCAPE_MODE_DATA 0x01c
+#define TEGRA_CSI_CIL_SW_SENSOR_RESET 0x020
+
+/* CSI Pattern Generator registers: Starts from 0x9c4, offset 0x18c */
+#define TEGRA_CSI_TPG_OFFSET 0x18c
+
+#define TEGRA_CSI_PATTERN_GENERATOR_CTRL 0x000
+#define PG_MODE_OFFSET 2
+#define PG_ENABLE 0x1
+
+#define TEGRA_CSI_PG_BLANK 0x004
+#define TEGRA_CSI_PG_PHASE 0x008
+#define TEGRA_CSI_PG_RED_FREQ 0x00c
+#define PG_RED_VERT_INIT_FREQ_OFFSET 16
+#define PG_RED_HOR_INIT_FREQ_OFFSET 0
+
+#define TEGRA_CSI_PG_RED_FREQ_RATE 0x010
+#define TEGRA_CSI_PG_GREEN_FREQ 0x014
+#define PG_GREEN_VERT_INIT_FREQ_OFFSET 16
+#define PG_GREEN_HOR_INIT_FREQ_OFFSET 0
+
+#define TEGRA_CSI_PG_GREEN_FREQ_RATE 0x018
+#define TEGRA_CSI_PG_BLUE_FREQ 0x01c
+#define PG_BLUE_VERT_INIT_FREQ_OFFSET 16
+#define PG_BLUE_HOR_INIT_FREQ_OFFSET 0
+
+#define TEGRA_CSI_PG_BLUE_FREQ_RATE 0x020
+#define TEGRA_CSI_PG_AOHDR 0x024
+
+#define TEGRA_CSI_DPCM_CTRL_A 0xa2c
+#define TEGRA_CSI_DPCM_CTRL_B 0xa30
+
+/* Other CSI registers: Starts from 0xa44, offset 0x20c */
+#define TEGRA_CSI_STALL_COUNTER 0x20c
+#define TEGRA_CSI_CSI_READONLY_STATUS 0x210
+#define TEGRA_CSI_CSI_SW_STATUS_RESET 0x214
+#define TEGRA_CSI_CLKEN_OVERRIDE 0x218
+#define TEGRA_CSI_DEBUG_CONTROL 0x21c
+#define TEGRA_CSI_DEBUG_COUNTER_0 0x220
+#define TEGRA_CSI_DEBUG_COUNTER_1 0x224
+#define TEGRA_CSI_DEBUG_COUNTER_2 0x228
+
+
+/* CSI Pixel Parser registers */
+#define TEGRA_CSI_PIXEL_PARSER_0_BASE 0x0838
+#define TEGRA_CSI_PIXEL_PARSER_1_BASE 0x086c
+#define TEGRA_CSI_PIXEL_PARSER_2_BASE 0x1038
+#define TEGRA_CSI_PIXEL_PARSER_3_BASE 0x106c
+#define TEGRA_CSI_PIXEL_PARSER_4_BASE 0x1838
+#define TEGRA_CSI_PIXEL_PARSER_5_BASE 0x186c
+
+/* CSIA to CSIB register offset */
+#define TEGRA_CSI_PORT_OFFSET 0x34
+
+#endif
#include <linux/of_graph.h>
#include <linux/platform_device.h>
+#include <media/media-entity.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-ctrls.h>
+#include <media/camera_common.h>
+
+#include "dev.h"
+#include "vi/vi.h"
#include "csi.h"
-#include "../camera/core.h"
-/* -----------------------------------------------------------------------------
- * V4L2 Subdevice Video Operations
+
+#define DEBUG 0
+
+static void csi_write(struct tegra_csi_device *csi, unsigned int addr,
+ u32 val, u8 port)
+{
+#if DEBUG
+ dev_info(csi->dev, "%s:port %d offset 0x%08x val:0x%08x\n",
+ __func__, port, addr, val);
+#endif
+ writel(val, (csi->iomem[port] + addr));
+}
+
+static u32 csi_read(struct tegra_csi_device *csi, unsigned int addr,
+ u8 port)
+{
+#if DEBUG
+ dev_info(csi->dev, "%s:port %d offset 0x%08x\n", __func__, port, addr);
+#endif
+ return readl((csi->iomem[port] + addr));
+}
+
+/* Pixel parser registers accessors */
+static void pp_write(struct tegra_csi_port *port, u32 addr, u32 val)
+{
+#if DEBUG
+ pr_info("%s:offset 0x%08x val:0x%08x\n", __func__, addr, val);
+#endif
+ writel(val, port->pixel_parser + addr);
+}
+
+static u32 pp_read(struct tegra_csi_port *port, u32 addr)
+{
+#if DEBUG
+ pr_info("%s:offset 0x%08x\n", __func__, addr);
+#endif
+ return readl(port->pixel_parser + addr);
+}
+
+/* CSI CIL registers accessors */
+static void cil_write(struct tegra_csi_port *port, u32 addr, u32 val)
+{
+#if DEBUG
+ pr_info("%s:offset 0x%08x val:0x%08x\n", __func__, addr, val);
+#endif
+ writel(val, port->cil + addr);
+}
+
+static u32 cil_read(struct tegra_csi_port *port, u32 addr)
+{
+#if DEBUG
+ pr_info("%s:offset 0x%08x\n", __func__, addr);
+#endif
+ return readl(port->cil + addr);
+}
+
+/* Test pattern generator registers accessor */
+static void tpg_write(struct tegra_csi_port *port, unsigned int addr, u32 val)
+{
+ writel(val, port->tpg + addr);
+}
+
+static int csi_get_clks(struct tegra_csi_device *csi,
+ struct platform_device *pdev)
+{
+ csi->clk = devm_clk_get(&pdev->dev, "csi");
+ if (IS_ERR(csi->clk)) {
+ dev_err(&pdev->dev, "Failed to get csi clock\n");
+ return PTR_ERR(csi->clk);
+ }
+
+ csi->tpg_clk = devm_clk_get(&pdev->dev, "pll_d");
+ if (IS_ERR(csi->tpg_clk)) {
+ dev_err(&pdev->dev, "Failed to get tpg clock\n");
+ return PTR_ERR(csi->tpg_clk);
+ }
+
+ csi->cil[0] = devm_clk_get(&pdev->dev, "cilab");
+ if (IS_ERR(csi->cil[0])) {
+ dev_err(&pdev->dev, "Failed to get cilab clock\n");
+ return PTR_ERR(csi->cil[0]);
+ }
+
+ csi->cil[1] = devm_clk_get(&pdev->dev, "cilcd");
+ if (IS_ERR(csi->cil[1])) {
+ dev_err(&pdev->dev, "Failed to get cilcd clock\n");
+ return PTR_ERR(csi->cil[1]);
+ }
+
+ csi->cil[2] = devm_clk_get(&pdev->dev, "cile");
+ if (IS_ERR(csi->cil[2])) {
+ dev_err(&pdev->dev, "Failed to get cile clock\n");
+ return PTR_ERR(csi->cil[2]);
+ }
+
+ return 0;
+}
+
+static int set_csi_properties(struct tegra_csi_device *csi,
+ struct platform_device *pdev)
+{
+ struct camera_common_data *s_data = &csi->s_data;
+
+ csi->pg_mode = 0;
+ /*
+ * These values are only used for tpg mode
+ * With sensor, CSI power and clock info are provided
+ * by the sensor sub device
+ */
+ s_data->csi_port = 0;
+ s_data->numlanes = 12;
+ s_data->def_clk_freq = 102000000;
+
+ if (!csi->ports) {
+ int port_num = (s_data->numlanes >> 1);
+ csi->ports = devm_kzalloc(&pdev->dev,
+ (port_num * sizeof(struct tegra_csi_port)),
+ GFP_KERNEL);
+ if (!csi->ports)
+ return -ENOMEM;
+ csi->num_ports = port_num;
+ }
+
+ return 0;
+}
+
+void set_csi_portinfo(struct tegra_csi_device *csi,
+ unsigned int port, unsigned int numlanes)
+{
+ struct camera_common_data *s_data = &csi->s_data;
+
+ s_data->csi_port = port;
+ s_data->numlanes = numlanes;
+ csi->ports[port].lanes = numlanes;
+}
+EXPORT_SYMBOL(set_csi_portinfo);
+
+static void set_csi_registers(struct tegra_csi_device *csi,
+ void __iomem *regbase)
+{
+ int i, j, idx;
+
+ csi->iomem[0] = (regbase + TEGRA_CSI_PIXEL_PARSER_0_BASE);
+ csi->iomem[1] = (regbase + TEGRA_CSI_PIXEL_PARSER_2_BASE);
+ csi->iomem[2] = (regbase + TEGRA_CSI_PIXEL_PARSER_4_BASE);
+
+ for (j = 0; j < 3; j++) {
+ for (i = 0; i < 2; i++) {
+ idx = (j << 1) + i;
+ /* Initialize port register bases */
+ csi->ports[idx].pixel_parser = csi->iomem[j] +
+ i * TEGRA_CSI_PORT_OFFSET;
+ csi->ports[idx].cil = csi->iomem[j] +
+ TEGRA_CSI_CIL_OFFSET +
+ i * TEGRA_CSI_PORT_OFFSET;
+ csi->ports[idx].tpg = csi->iomem[j] +
+ TEGRA_CSI_TPG_OFFSET +
+ i * TEGRA_CSI_PORT_OFFSET;
+
+ csi->ports[idx].num = idx;
+ csi->ports[idx].lanes = 2;
+ }
+ }
+}
+
+static int clock_start(struct clk *clk, unsigned int freq)
+{
+ int err = 0;
+
+ err = clk_prepare_enable(clk);
+ if (err)
+ pr_err("csi clk enable error\n");
+ err = clk_set_rate(clk, freq);
+ if (err)
+ pr_err("cil clk set error\n");
+
+ return err;
+}
+
+int tegra_csi_power(struct tegra_csi_device *csi, int port_num, int enable)
+{
+ int err = 0;
+ int port = port_num >> 1;
+ struct camera_common_data *s_data = &csi->s_data;
+
+
+ if (enable) {
+ /* set clk and power */
+ err = clk_prepare_enable(csi->clk);
+ if (err)
+ pr_err("csi clk error\n");
+
+ err = clock_start(csi->cil[port], s_data->def_clk_freq);
+ if (err)
+ pr_err("cil clk error\n");
+
+ if (csi->pg_mode) {
+ err = clock_start(csi->tpg_clk, 927000000);
+ if (err)
+ pr_err("tpg clk set error\n");
+ else {
+ tegra_clk_cfg_ex(csi->tpg_clk,
+ TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
+ tegra_clk_cfg_ex(csi->tpg_clk,
+ TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
+ tegra_clk_cfg_ex(csi->tpg_clk,
+ TEGRA_CLK_MIPI_CSI_OUT_ENB, 0);
+ }
+ }
+ camera_common_dpd_disable(s_data);
+ } else {
+ camera_common_dpd_enable(s_data);
+ clk_disable_unprepare(csi->cil[port]);
+ clk_disable_unprepare(csi->clk);
+
+ if (csi->pg_mode) {
+ tegra_clk_cfg_ex(csi->tpg_clk,
+ TEGRA_CLK_MIPI_CSI_OUT_ENB, 1);
+ tegra_clk_cfg_ex(csi->tpg_clk,
+ TEGRA_CLK_PLLD_CSI_OUT_ENB, 0);
+ tegra_clk_cfg_ex(csi->tpg_clk,
+ TEGRA_CLK_PLLD_DSI_OUT_ENB, 0);
+ clk_disable_unprepare(csi->tpg_clk);
+ }
+ }
+
+ return err;
+}
+EXPORT_SYMBOL(tegra_csi_power);
+
+/*
+ * -----------------------------------------------------------------------------
+ * CSI Subdevice Video Operations
+ * -----------------------------------------------------------------------------
*/
+void tegra_csi_start_streaming(struct tegra_csi_device *csi,
+ enum tegra_csi_port_num port_num)
+{
+ struct tegra_csi_port *port = &csi->ports[port_num];
+
+ csi_write(csi, TEGRA_CSI_CLKEN_OVERRIDE, 0, port_num>>1);
+
+ /* Clean up status */
+ pp_write(port, TEGRA_CSI_PIXEL_PARSER_STATUS, 0xFFFFFFFF);
+ cil_write(port, TEGRA_CSI_CIL_STATUS, 0xFFFFFFFF);
+ cil_write(port, TEGRA_CSI_CILX_STATUS, 0xFFFFFFFF);
+
+ cil_write(port, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0);
+
+ /* CIL PHY registers setup */
+ cil_write(port, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0);
+ cil_write(port, TEGRA_CSI_CIL_PHY_CONTROL, 0xA);
+
+ /*
+ * The CSI unit provides for connection of up to six cameras in
+ * the system and is organized as three identical instances of
+ * two MIPI support blocks, each with a separate 4-lane
+ * interface that can be configured as a single camera with 4
+ * lanes or as a dual camera with 2 lanes available for each
+ * camera.
+ */
+ if (port->lanes == 4) {
+ int port_val = ((port_num >> 1) << 1);
+ struct tegra_csi_port *port_a = &csi->ports[port_val];
+ struct tegra_csi_port *port_b = &csi->ports[port_val+1];
+
+ cil_write(port_a, TEGRA_CSI_CIL_PAD_CONFIG0,
+ BRICK_CLOCK_A_4X);
+ cil_write(port_b, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0);
+ cil_write(port_b, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0);
+ cil_write(port_a, TEGRA_CSI_CIL_PHY_CONTROL, 0xA);
+ cil_write(port_b, TEGRA_CSI_CIL_PHY_CONTROL, 0xA);
+ csi_write(csi, TEGRA_CSI_PHY_CIL_COMMAND,
+ CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_ENABLE,
+ port_num>>1);
+ } else {
+ u32 val = csi_read(csi, TEGRA_CSI_PHY_CIL_COMMAND, port_num>>1);
+
+ val |= ((port->num & 0x1) == PORT_A) ? CSI_A_PHY_CIL_ENABLE :
+ CSI_B_PHY_CIL_ENABLE;
+ csi_write(csi, TEGRA_CSI_PHY_CIL_COMMAND, val, port_num>>1);
+ }
+
+ /* CSI pixel parser registers setup */
+ pp_write(port, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
+ (0xF << CSI_PP_START_MARKER_FRAME_MAX_OFFSET) |
+ CSI_PP_SINGLE_SHOT_ENABLE | CSI_PP_RST);
+ pp_write(port, TEGRA_CSI_PIXEL_PARSER_INTERRUPT_MASK, 0x0);
+ pp_write(port, TEGRA_CSI_PIXEL_STREAM_CONTROL0,
+ CSI_PP_PACKET_HEADER_SENT |
+ CSI_PP_DATA_IDENTIFIER_ENABLE |
+ CSI_PP_WORD_COUNT_SELECT_HEADER |
+ CSI_PP_CRC_CHECK_ENABLE | CSI_PP_WC_CHECK |
+ CSI_PP_OUTPUT_FORMAT_STORE |
+ CSI_PP_HEADER_EC_DISABLE | CSI_PPA_PAD_FRAME_NOPAD |
+ (port->num & 1));
+ pp_write(port, TEGRA_CSI_PIXEL_STREAM_CONTROL1,
+ (0x1 << CSI_PP_TOP_FIELD_FRAME_OFFSET) |
+ (0x1 << CSI_PP_TOP_FIELD_FRAME_MASK_OFFSET));
+ pp_write(port, TEGRA_CSI_PIXEL_STREAM_GAP,
+ 0x14 << PP_FRAME_MIN_GAP_OFFSET);
+ pp_write(port, TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME, 0x0);
+ pp_write(port, TEGRA_CSI_INPUT_STREAM_CONTROL,
+ (0x3f << CSI_SKIP_PACKET_THRESHOLD_OFFSET) |
+ (port->lanes - 1));
+
+ /* Test Pattern Generator setup */
+ if (csi->pg_mode) {
+ tpg_write(port, TEGRA_CSI_PATTERN_GENERATOR_CTRL,
+ ((csi->pg_mode - 1) << PG_MODE_OFFSET) |
+ PG_ENABLE);
+ tpg_write(port, TEGRA_CSI_PG_PHASE, 0x0);
+ tpg_write(port, TEGRA_CSI_PG_RED_FREQ,
+ (0x10 << PG_RED_VERT_INIT_FREQ_OFFSET) |
+ (0x10 << PG_RED_HOR_INIT_FREQ_OFFSET));
+ tpg_write(port, TEGRA_CSI_PG_RED_FREQ_RATE, 0x0);
+ tpg_write(port, TEGRA_CSI_PG_GREEN_FREQ,
+ (0x10 << PG_GREEN_VERT_INIT_FREQ_OFFSET) |
+ (0x10 << PG_GREEN_HOR_INIT_FREQ_OFFSET));
+ tpg_write(port, TEGRA_CSI_PG_GREEN_FREQ_RATE, 0x0);
+ tpg_write(port, TEGRA_CSI_PG_BLUE_FREQ,
+ (0x10 << PG_BLUE_VERT_INIT_FREQ_OFFSET) |
+ (0x10 << PG_BLUE_HOR_INIT_FREQ_OFFSET));
+ tpg_write(port, TEGRA_CSI_PG_BLUE_FREQ_RATE, 0x0);
+ }
+
+#if DEBUG
+ /* 0x454140E1 - register setting for line counter */
+ pp_write(port, TEGRA_CSI_DEBUG_CONTROL, 0x454140E1);
+#endif
+ pp_write(port, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
+ (0xF << CSI_PP_START_MARKER_FRAME_MAX_OFFSET) |
+ CSI_PP_SINGLE_SHOT_ENABLE | CSI_PP_ENABLE);
+}
+EXPORT_SYMBOL(tegra_csi_start_streaming);
+
+void tegra_csi_status(struct tegra_csi_device *csi,
+ enum tegra_csi_port_num port_num)
+{
+ struct tegra_csi_port *port = &csi->ports[port_num];
+ u32 val = pp_read(port, TEGRA_CSI_PIXEL_PARSER_STATUS);
+
+ dev_info(csi->dev, "TEGRA_CSI_PIXEL_PARSER_STATUS 0x%08x\n",
+ val);
+
+ val = cil_read(port, TEGRA_CSI_CIL_STATUS);
+ dev_info(csi->dev, "TEGRA_CSI_CIL_STATUS 0x%08x\n", val);
+
+ val = cil_read(port, TEGRA_CSI_CILX_STATUS);
+ dev_info(csi->dev, "TEGRA_CSI_CILX_STATUS 0x%08x\n", val);
+
+#if DEBUG
+ val = pp_read(port, TEGRA_CSI_DEBUG_COUNTER_0);
+ dev_info(csi->dev, "TEGRA_CSI_DEBUG_COUNTER_0 0x%08x\n", val);
+ val = pp_read(port, TEGRA_CSI_DEBUG_COUNTER_1);
+ dev_info(csi->dev, "TEGRA_CSI_DEBUG_COUNTER_1 0x%08x\n", val);
+ val = pp_read(port, TEGRA_CSI_DEBUG_COUNTER_2);
+ dev_info(csi->dev, "TEGRA_CSI_DEBUG_COUNTER_2 0x%08x\n", val);
+#endif
+}
+EXPORT_SYMBOL(tegra_csi_status);
+
+void tegra_csi_stop_streaming(struct tegra_csi_device *csi,
+ enum tegra_csi_port_num port_num)
+{
+ struct tegra_csi_port *port = &csi->ports[port_num];
+
+ tegra_csi_status(csi, port_num);
+
+ pp_write(port, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
+ (0xF << CSI_PP_START_MARKER_FRAME_MAX_OFFSET) |
+ CSI_PP_DISABLE);
+}
+EXPORT_SYMBOL(tegra_csi_stop_streaming);
+
static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable)
{
- /* Need programming CSI only for VI mode */
+ struct tegra_csi_device *csi = to_csi(subdev);
+ struct tegra_channel *chan = subdev->host_priv;
+ enum tegra_csi_port_num port_num = (chan->port & 1) ? PORT_B : PORT_A;
+
+ if (enable)
+ tegra_csi_start_streaming(csi, port_num);
+ else
+ tegra_csi_stop_streaming(csi, port_num);
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * V4L2 Subdevice Pad Operations
+ */
+
+static struct v4l2_mbus_framefmt *
+__tegra_csi_get_pad_format(struct tegra_csi_device *csi,
+ struct v4l2_subdev_pad_config *cfg,
+ unsigned int pad, u32 which)
+{
+ enum tegra_csi_port_num port_num = (pad >> 1);
+
+ switch (which) {
+ case V4L2_SUBDEV_FORMAT_TRY:
+#if defined(CONFIG_VIDEO_V4L2_SUBDEV_API)
+ return v4l2_subdev_get_try_format(&csi->subdev, cfg, pad);
+#endif
+ case V4L2_SUBDEV_FORMAT_ACTIVE:
+ return &csi->ports[port_num].format;
+ default:
+ return NULL;
+ }
+}
+
+static int tegra_csi_get_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct tegra_csi_device *csi = to_csi(subdev);
+
+ fmt->format = *__tegra_csi_get_pad_format(csi, cfg,
+ fmt->pad, fmt->which);
+ return 0;
+}
+
+static int tegra_csi_set_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct tegra_csi_device *csi = to_csi(subdev);
+ struct v4l2_mbus_framefmt *__format;
+ enum tegra_csi_port_num port_num = (fmt->pad >> 1);
+
+ __format = __tegra_csi_get_pad_format(csi, cfg,
+ fmt->pad, fmt->which);
+ if (__format)
+ csi->ports[port_num].format = *__format;
+
return 0;
}
.s_stream = tegra_csi_s_stream,
};
+static struct v4l2_subdev_pad_ops tegra_csi_pad_ops = {
+ .get_fmt = tegra_csi_get_format,
+ .set_fmt = tegra_csi_set_format,
+};
+
static struct v4l2_subdev_ops tegra_csi_ops = {
.video = &tegra_csi_video_ops,
+ .pad = &tegra_csi_pad_ops,
};
/* -----------------------------------------------------------------------------
return 0;
}
+int tegra_csi_init(struct tegra_csi_device *csi,
+ struct platform_device *pdev)
+{
+ int err = 0;
+ struct nvhost_device_data *pdata = pdev->dev.platform_data;
+
+ csi->dev = &pdev->dev;
+ err = set_csi_properties(csi, pdev);
+ if (err)
+ return err;
+
+ set_csi_registers(csi, pdata->aperture[0]);
+
+ err = csi_get_clks(csi, pdev);
+ if (err)
+ dev_err(&pdev->dev, "Failed to get CSI clks\n");
+
+ return err;
+}
+EXPORT_SYMBOL(tegra_csi_init);
+
int tegra_csi_media_controller_init(struct tegra_csi_device *csi,
struct platform_device *pdev)
{
if (ret < 0)
return ret;
+ ret = tegra_csi_init(csi, pdev);
+ if (ret < 0)
+ return ret;
+
/* Initialize V4L2 subdevice and media entity */
subdev = &csi->subdev;
v4l2_subdev_init(subdev, &tegra_csi_ops);
csi->ports[i].format.width = TEGRA_DEF_WIDTH;
csi->ports[i].format.height = TEGRA_DEF_HEIGHT;
- csi->ports[i].num = i;
-
csi->pads[i * 2].flags = MEDIA_PAD_FL_SINK;
csi->pads[i * 2 + 1].flags = MEDIA_PAD_FL_SOURCE;
}
media_entity_cleanup(&subdev->entity);
return ret;
}
+EXPORT_SYMBOL(tegra_csi_media_controller_init);
int tegra_csi_media_controller_remove(struct tegra_csi_device *csi)
{
media_entity_cleanup(&subdev->entity);
return 0;
}
+EXPORT_SYMBOL(tegra_csi_media_controller_remove);
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
+#include <media/camera_common.h>
+#include "../camera/registers.h"
+
enum tegra_csi_port_num {
PORT_A = 0,
PORT_B = 1,
PORT_F = 5,
};
+#define csi_port_is_valid(port) \
+ (port < PORT_A ? 0 : (port > PORT_F ? 0 : 1))
+
struct tegra_csi_port {
void __iomem *pixel_parser;
void __iomem *cil;
struct tegra_csi_device {
struct v4l2_subdev subdev;
struct device *dev;
- void __iomem *iomem;
+ void __iomem *iomem[3];
struct clk *clk;
+ struct clk *tpg_clk;
+ struct clk *cil[3];
+ struct camera_common_data s_data;
struct tegra_csi_port *ports;
struct media_pad *pads;
int num_ports;
+ int pg_mode;
};
static inline struct tegra_csi_device *to_csi(struct v4l2_subdev *subdev)
return container_of(subdev, struct tegra_csi_device, subdev);
}
+void set_csi_portinfo(struct tegra_csi_device *csi,
+ unsigned int port, unsigned int numlanes);
+void tegra_csi_status(struct tegra_csi_device *csi,
+ enum tegra_csi_port_num port_num);
+void tegra_csi_start_streaming(struct tegra_csi_device *csi,
+ enum tegra_csi_port_num port_num);
+void tegra_csi_stop_streaming(struct tegra_csi_device *csi,
+ enum tegra_csi_port_num port_num);
+int tegra_csi_power(struct tegra_csi_device *csi, int port, int enable);
+int tegra_csi_init(struct tegra_csi_device *csi,
+ struct platform_device *pdev);
int tegra_csi_media_controller_init(struct tegra_csi_device *csi,
struct platform_device *pdev);
int tegra_csi_media_controller_remove(struct tegra_csi_device *csi);
struct nvhost_device_data *pdata =
container_of(nb, struct nvhost_device_data,
toggle_slcg_notifier);
+ struct vi *tegra_vi = (struct vi *)pdata->private_data;
+
+ if (tegra_vi->mc_vi.pg_mode)
+ return NOTIFY_OK;
clk = clk_get(&pdata->pdev->dev, "pll_d");
if (IS_ERR(clk))
err = tegra_vi_init_mfi(&tegra_vi->mfi_ctx, num_channels);
if (err)
goto vi_probe_fail;
+
+ if (!pdata->aperture[0]) {
+ dev_err(&dev->dev, "%s: failed to map register base\n",
+ __func__);
+ return -ENXIO;
+ }
/* call vi_intr_init and stats_work */
INIT_WORK(&tegra_vi->stats_work, vi_stats_worker);
if (err)
goto camera_unregister;
+ err = tegra_csi_init(&tegra_vi->csi, dev);
+ if (err)
+ goto vi_mc_init_error;
+
+ tegra_vi->mc_vi.csi = &tegra_vi->csi;
+ tegra_vi->mc_vi.reg = tegra_vi->reg;
err = tegra_vi_media_controller_init(&tegra_vi->mc_vi, dev);
if (err)
goto vi_mc_init_error;
struct device *dev;
struct nvhost_device_data *ndata;
struct tegra_mc_vi mc_vi;
+ struct tegra_csi_device csi;
struct regulator *reg;
struct dentry *debugdir;
+++ /dev/null
-/*
- * drivers/media/platform/tegra/camera/mc_common.h
- *
- * Tegra Media controller common APIs
- *
- * Copyright (c) 2012-2016, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __MC_COMMON_H__
-#define __MC_COMMON_H__
-
-#include <media/media-device.h>
-#include <media/media-entity.h>
-#include <media/v4l2-async.h>
-#include <media/v4l2-ctrls.h>
-#include <media/v4l2-device.h>
-#include <media/v4l2-dev.h>
-#include <media/videobuf2-core.h>
-
-#define MAX_FORMAT_NUM 64
-#define MAX_SUBDEVICES 4
-
-/**
- * struct tegra_channel_buffer - video channel buffer
- * @buf: vb2 buffer base object
- * @queue: buffer list entry in the channel queued buffers list
- * @chan: channel that uses the buffer
- * @addr: Tegra IOVA buffer address for VI output
- */
-struct tegra_channel_buffer {
- struct vb2_buffer buf;
- struct list_head queue;
- struct tegra_channel *chan;
-
- dma_addr_t addr;
-};
-
-#define to_tegra_channel_buffer(vb) \
- container_of(vb, struct tegra_channel_buffer, buf)
-
-/**
- * struct tegra_vi_graph_entity - Entity in the video graph
- * @list: list entry in a graph entities list
- * @node: the entity's DT node
- * @entity: media entity, from the corresponding V4L2 subdev
- * @asd: subdev asynchronous registration information
- * @subdev: V4L2 subdev
- */
-struct tegra_vi_graph_entity {
- struct list_head list;
- struct device_node *node;
- struct media_entity *entity;
-
- struct v4l2_async_subdev asd;
- struct v4l2_subdev *subdev;
-};
-
-/**
- * struct tegra_channel - Tegra video channel
- * @list: list entry in a composite device dmas list
- * @video: V4L2 video device associated with the video channel
- * @video_lock:
- * @pad: media pad for the video device entity
- * @pipe: pipeline belonging to the channel
- *
- * @vi: composite device DT node port number for the channel
- *
- * @kthread_capture: kernel thread task structure of this video channel
- * @wait: wait queue structure for kernel thread
- *
- * @format: active V4L2 pixel format
- * @fmtinfo: format information corresponding to the active @format
- *
- * @queue: vb2 buffers queue
- * @alloc_ctx: allocation context for the vb2 @queue
- * @sequence: V4L2 buffers sequence number
- *
- * @capture: list of queued buffers for capture
- * @queued_lock: protects the buf_queued list
- *
- * @csi: CSI register bases
- * @align: channel buffer alignment, default is 64
- * @port: CSI port of this video channel
- * @io_id: Tegra IO rail ID of this video channel
- *
- * @fmts_bitmap: a bitmap for formats supported
- * @bypass: bypass flag for VI bypass mode
- */
-struct tegra_channel {
- struct list_head list;
- struct video_device video;
- struct media_pad pad;
- struct media_pipeline pipe;
-
- struct tegra_mc_vi *vi;
- struct v4l2_subdev *subdev[MAX_SUBDEVICES];
-
- struct v4l2_ctrl_handler ctrl_handler;
- struct v4l2_pix_format format;
- const struct tegra_video_format *fmtinfo;
-
- struct vb2_queue queue;
- void *alloc_ctx;
-
- void __iomem *csi;
- unsigned int align;
- unsigned int port;
- unsigned int io_id;
- unsigned int num_subdevs;
-
- DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM);
- bool bypass;
-};
-
-#define to_tegra_channel(vdev) \
- container_of(vdev, struct tegra_channel, video)
-
-enum tegra_vi_pg_mode {
- TEGRA_VI_PG_DISABLED = 0,
- TEGRA_VI_PG_DIRECT,
- TEGRA_VI_PG_PATCH,
-};
-
-/**
- * struct tegra_mc_vi - NVIDIA Tegra Media controller structure
- * @v4l2_dev: V4L2 device
- * @media_dev: media device
- * @dev: device struct
- * @tegra_camera: tegra camera structure
- * @nvhost_device_data: NvHost VI device information
- *
- * @notifier: V4L2 asynchronous subdevs notifier
- * @entities: entities in the graph as a list of tegra_vi_graph_entity
- * @num_subdevs: number of subdevs in the pipeline
- *
- * @channels: list of channels at the pipeline output and input
- *
- * @ctrl_handler: V4L2 control handler
- * @pattern: test pattern generator V4L2 control
- * @pg_mode: test pattern generator mode (disabled/direct/patch)
- * @tpg_fmts_bitmap: a bitmap for formats in test pattern generator mode
- *
- * @has_sensors: a flag to indicate whether is a real sensor connecting
- */
-struct tegra_mc_vi {
- struct platform_device *ndev;
- struct v4l2_device v4l2_dev;
- struct media_device media_dev;
- struct device *dev;
- struct nvhost_device_data *ndata;
-
- struct v4l2_async_notifier notifier;
- struct list_head entities;
- unsigned int num_channels;
- unsigned int num_subdevs;
-
- struct tegra_channel *chans;
-
- struct v4l2_ctrl_handler ctrl_handler;
- struct v4l2_ctrl *pattern;
- enum tegra_vi_pg_mode pg_mode;
- DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM);
-
- bool has_sensors;
-};
-
-void tegra_vi_v4l2_cleanup(struct tegra_mc_vi *vi);
-int tegra_vi_v4l2_init(struct tegra_mc_vi *vi);
-int tegra_vi_graph_init(struct tegra_mc_vi *vi);
-void tegra_vi_graph_cleanup(struct tegra_mc_vi *vi);
-int tegra_vi_channels_init(struct tegra_mc_vi *vi);
-int tegra_vi_channels_cleanup(struct tegra_mc_vi *vi);
-void tegra_channel_fmts_bitmap_init(struct tegra_channel *chan,
- struct tegra_vi_graph_entity *entity);
-int tegra_vi_media_controller_init(struct tegra_mc_vi *mc_vi,
- struct platform_device *pdev);
-void tegra_vi_media_controller_cleanup(struct tegra_mc_vi *mc_vi);
-#endif
projects / hercules2020 / nv-tegra / linux-4.4.git / commitdiff