Issue: EQOS trying to access the PHY registers through
mdiobus_write/read from the phy_change IRQ handler.
At this stage PHY is not in proper state to respond
to the register read/write which leads to below timeout -
[ 18.116266] Decoded FIFO Entry: 0
[ 18.116267] Direction: READ
[ 18.116268] Bridge ID: 0x9
[ 18.116270] Error Type: 0x12 -- Timeout error
[ 18.116271] Length: 0
[ 18.116274] Protection: 0x2 -- Unprivileged, Non-Secure, Data Access
[ 18.116276] Source ID: 0x1 -- CCPLEX
[ 18.116277] AXI_ID: 0x4 -- A57 Core 0
[ 18.116279] Cache: 0x1 -- Device
[ 18.116280] Burst: 0x1
[ 18.116310] Address: 0x2490200 (Unknown Device)
Fix: Start the PHY while bringup the interface and
stop the PHY while the interface is going down.
Bug
200284385
Change-Id: Ib557f49b11f857f214b245e0284e045c8b4981d9
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: http://git-master/r/
1488009
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Tested-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>