mmc: tegra: Parse dt node for ddr_trim_delay property

Add support for parsing ddr_trim_delay property from
dt node.

Change-Id: If61b72f09544c1b327258ebfd570211751614af7
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/739529
Reviewed-by: Automatic_Commit_Validation_User

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index d7d19562f2783d8ce6203c2b35ea91bcd255361a..2579b6e8116acc2b2de9047e923f3bce1feb20d3 100644 (file)
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -912,6 +912,7 @@ static int sdhci_tegra_parse_dt(struct device *dev)
 
        of_property_read_u32(np, "tap-delay", &plat->tap_delay);
        of_property_read_u32(np, "trim-delay", &plat->trim_delay);
+       of_property_read_u32(np, "ddr-trim-delay", &plat->ddr_trim_delay);
        of_property_read_u32(np, "ddr-clk-limit", &plat->ddr_clk_limit);
        of_property_read_u32(np, "max-clk-limit", &plat->max_clk_limit);
        of_property_read_u32(np, "uhs_mask", &plat->uhs_mask);