Skip host clk gating during voltage switching to avoid hangs related
to register accesses without clock.
Bug
200203279
Change-Id: If5c723cd38eec3366c696e7d5405e7ffeb8b0b7c
Signed-off-by: Anubhav Jain <anubhavj@nvidia.com>
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/
1181921
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
* for 5 ms according to the SD spec
*/
clock = host->ios.clock;
+ host->skip_host_clkgate = true;
host->ios.clock = 0;
mmc_set_ios(host);
* sent CMD11, so a power cycle is required anyway
*/
err = -EAGAIN;
+ host->skip_host_clkgate = false;
goto power_cycle;
}
/* Keep clock gated for at least 10 ms, though spec only says 5 ms */
mmc_delay(10);
host->ios.clock = clock;
+ host->skip_host_clkgate = false;
mmc_set_ios(host);
/* Wait for at least 1 ms according to spec */
mmiowb();
spin_unlock_irqrestore(&host->lock, flags);
- if (!ios->clock && ios->clock != host->clock) {
+
+ if (!ios->clock && !host->mmc->skip_host_clkgate &&
+ (ios->clock != host->clock)) {
host->ops->set_clock(host, ios->clock);
host->clock = ios->clock;
}
mmc_pm_flag_t pm_caps; /* supported pm features */
+ bool skip_host_clkgate;
/* host specific block data */
unsigned int max_seg_size; /* see blk_queue_max_segment_size */
unsigned short max_segs; /* see blk_queue_max_segments */