clk: tegra: init sdmmc1 and sdmmc2 clock

Change-Id: I556f597dc8c11e6941ded65acd1c7e83db023ca8
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1226255
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index d8bbae500f5b65fd59813dc960fb9bd77b3c55db..f1b114d8623987939a644ebc242231b2645e8937 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3393,6 +3393,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
        { TEGRA210_CLK_MC_CBPA, TEGRA210_CLK_CLK_MAX, 0, 1},
        { TEGRA210_CLK_MC_CCPA, TEGRA210_CLK_CLK_MAX, 0, 1},
        { TEGRA210_CLK_MC_CDPA, TEGRA210_CLK_CLK_MAX, 0, 1},
+       { TEGRA210_CLK_SDMMC1, TEGRA210_CLK_PLL_P, 204000000, 0},
+       { TEGRA210_CLK_SDMMC2, TEGRA210_CLK_PLL_P, 204000000, 0},
        /* This MUST be the last entry. */
        { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
 };