clk: tegra: fix gm20b.gbus user mode

Fix gm20b.gbus client so that it can set a floor on the shared clk
"gbus" and allow it to set the gpu clock frequency.

Bug 200233943

Change-Id: If751e05d4f9e5a221b72182b9f7f7e9c575f5d04
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1277371
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra-shared.c b/drivers/clk/tegra/clk-tegra-shared.c
index 081d33442e96748fe82497063a88e9941ed9c89e..cea77b68781cbbdedb92c34f0f8e00803b459a56 100644 (file)
--- a/drivers/clk/tegra/clk-tegra-shared.c
+++ b/drivers/clk/tegra/clk-tegra-shared.c
@@ -123,7 +123,7 @@ static struct tegra_shared_clk shared_clks[] = {
        SHARED_CLK("vic.shared_emc", "emc_master", SHARED_BW, 0, 0, NULL, tegra_clk_vic_shared_emc),
        SHARED_CLK("ape.emc", "emc_master", 0, 0, 0, NULL, tegra_clk_ape_emc),
        SHARED_CLK("pcie.emc", "emc_master", 0, 0, 0, NULL, tegra_clk_pcie_emc),
-       SHARED_CLK("gm20b.gbus", "gbus", SHARED_CEILING, 0, 0, NULL, tegra_clk_gm20b_gbus),
+       SHARED_CLK("gm20b.gbus", "gbus", 0, 0, 0, NULL, tegra_clk_gm20b_gbus),
        SHARED_CLK("cap.gbus", "gbus", SHARED_CEILING, 0, 0, NULL, tegra_clk_cap_gbus),
        SHARED_CLK("edp.gbus", "gbus", SHARED_CEILING, 0, 0, NULL, tegra_clk_edp_gbus),
        SHARED_CLK("cap.vgpu.gbus", "gbus", SHARED_CEILING, 0, 0, NULL, tegra_clk_cap_vgpu_gbus),