2 * Omnivision OV2659 CMOS Image Sensor driver
4 * Copyright (C) 2015 Texas Instruments, Inc.
6 * Benoit Parrot <bparrot@ti.com>
7 * Lad, Prabhakar <prabhakar.csengg@gmail.com>
9 * This program is free software; you may redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
15 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
17 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
18 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/media.h>
32 #include <linux/module.h>
34 #include <linux/of_graph.h>
35 #include <linux/slab.h>
36 #include <linux/uaccess.h>
37 #include <linux/videodev2.h>
39 #include <media/media-entity.h>
40 #include <media/ov2659.h>
41 #include <media/v4l2-common.h>
42 #include <media/v4l2-ctrls.h>
43 #include <media/v4l2-device.h>
44 #include <media/v4l2-event.h>
45 #include <media/v4l2-image-sizes.h>
46 #include <media/v4l2-mediabus.h>
47 #include <media/v4l2-of.h>
48 #include <media/v4l2-subdev.h>
49 #include <asm/barrier.h>
51 #define DRIVER_NAME "ov2659"
54 * OV2659 register definitions
56 #define REG_SOFTWARE_STANDBY 0x0100
57 #define REG_SOFTWARE_RESET 0x0103
58 #define REG_IO_CTRL00 0x3000
59 #define REG_IO_CTRL01 0x3001
60 #define REG_IO_CTRL02 0x3002
61 #define REG_OUTPUT_VALUE00 0x3008
62 #define REG_OUTPUT_VALUE01 0x3009
63 #define REG_OUTPUT_VALUE02 0x300d
64 #define REG_OUTPUT_SELECT00 0x300e
65 #define REG_OUTPUT_SELECT01 0x300f
66 #define REG_OUTPUT_SELECT02 0x3010
67 #define REG_OUTPUT_DRIVE 0x3011
68 #define REG_INPUT_READOUT00 0x302d
69 #define REG_INPUT_READOUT01 0x302e
70 #define REG_INPUT_READOUT02 0x302f
72 #define REG_SC_PLL_CTRL0 0x3003
73 #define REG_SC_PLL_CTRL1 0x3004
74 #define REG_SC_PLL_CTRL2 0x3005
75 #define REG_SC_PLL_CTRL3 0x3006
76 #define REG_SC_CHIP_ID_H 0x300a
77 #define REG_SC_CHIP_ID_L 0x300b
78 #define REG_SC_PWC 0x3014
79 #define REG_SC_CLKRST0 0x301a
80 #define REG_SC_CLKRST1 0x301b
81 #define REG_SC_CLKRST2 0x301c
82 #define REG_SC_CLKRST3 0x301d
83 #define REG_SC_SUB_ID 0x302a
84 #define REG_SC_SCCB_ID 0x302b
86 #define REG_GROUP_ADDRESS_00 0x3200
87 #define REG_GROUP_ADDRESS_01 0x3201
88 #define REG_GROUP_ADDRESS_02 0x3202
89 #define REG_GROUP_ADDRESS_03 0x3203
90 #define REG_GROUP_ACCESS 0x3208
92 #define REG_AWB_R_GAIN_H 0x3400
93 #define REG_AWB_R_GAIN_L 0x3401
94 #define REG_AWB_G_GAIN_H 0x3402
95 #define REG_AWB_G_GAIN_L 0x3403
96 #define REG_AWB_B_GAIN_H 0x3404
97 #define REG_AWB_B_GAIN_L 0x3405
98 #define REG_AWB_MANUAL_CONTROL 0x3406
100 #define REG_TIMING_HS_H 0x3800
101 #define REG_TIMING_HS_L 0x3801
102 #define REG_TIMING_VS_H 0x3802
103 #define REG_TIMING_VS_L 0x3803
104 #define REG_TIMING_HW_H 0x3804
105 #define REG_TIMING_HW_L 0x3805
106 #define REG_TIMING_VH_H 0x3806
107 #define REG_TIMING_VH_L 0x3807
108 #define REG_TIMING_DVPHO_H 0x3808
109 #define REG_TIMING_DVPHO_L 0x3809
110 #define REG_TIMING_DVPVO_H 0x380a
111 #define REG_TIMING_DVPVO_L 0x380b
112 #define REG_TIMING_HTS_H 0x380c
113 #define REG_TIMING_HTS_L 0x380d
114 #define REG_TIMING_VTS_H 0x380e
115 #define REG_TIMING_VTS_L 0x380f
116 #define REG_TIMING_HOFFS_H 0x3810
117 #define REG_TIMING_HOFFS_L 0x3811
118 #define REG_TIMING_VOFFS_H 0x3812
119 #define REG_TIMING_VOFFS_L 0x3813
120 #define REG_TIMING_XINC 0x3814
121 #define REG_TIMING_YINC 0x3815
122 #define REG_TIMING_VERT_FORMAT 0x3820
123 #define REG_TIMING_HORIZ_FORMAT 0x3821
125 #define REG_FORMAT_CTRL00 0x4300
127 #define REG_VFIFO_READ_START_H 0x4608
128 #define REG_VFIFO_READ_START_L 0x4609
130 #define REG_DVP_CTRL02 0x4708
132 #define REG_ISP_CTRL00 0x5000
133 #define REG_ISP_CTRL01 0x5001
134 #define REG_ISP_CTRL02 0x5002
136 #define REG_LENC_RED_X0_H 0x500c
137 #define REG_LENC_RED_X0_L 0x500d
138 #define REG_LENC_RED_Y0_H 0x500e
139 #define REG_LENC_RED_Y0_L 0x500f
140 #define REG_LENC_RED_A1 0x5010
141 #define REG_LENC_RED_B1 0x5011
142 #define REG_LENC_RED_A2_B2 0x5012
143 #define REG_LENC_GREEN_X0_H 0x5013
144 #define REG_LENC_GREEN_X0_L 0x5014
145 #define REG_LENC_GREEN_Y0_H 0x5015
146 #define REG_LENC_GREEN_Y0_L 0x5016
147 #define REG_LENC_GREEN_A1 0x5017
148 #define REG_LENC_GREEN_B1 0x5018
149 #define REG_LENC_GREEN_A2_B2 0x5019
150 #define REG_LENC_BLUE_X0_H 0x501a
151 #define REG_LENC_BLUE_X0_L 0x501b
152 #define REG_LENC_BLUE_Y0_H 0x501c
153 #define REG_LENC_BLUE_Y0_L 0x501d
154 #define REG_LENC_BLUE_A1 0x501e
155 #define REG_LENC_BLUE_B1 0x501f
156 #define REG_LENC_BLUE_A2_B2 0x5020
158 #define REG_AWB_CTRL00 0x5035
159 #define REG_AWB_CTRL01 0x5036
160 #define REG_AWB_CTRL02 0x5037
161 #define REG_AWB_CTRL03 0x5038
162 #define REG_AWB_CTRL04 0x5039
163 #define REG_AWB_LOCAL_LIMIT 0x503a
164 #define REG_AWB_CTRL12 0x5049
165 #define REG_AWB_CTRL13 0x504a
166 #define REG_AWB_CTRL14 0x504b
168 #define REG_SHARPENMT_THRESH1 0x5064
169 #define REG_SHARPENMT_THRESH2 0x5065
170 #define REG_SHARPENMT_OFFSET1 0x5066
171 #define REG_SHARPENMT_OFFSET2 0x5067
172 #define REG_DENOISE_THRESH1 0x5068
173 #define REG_DENOISE_THRESH2 0x5069
174 #define REG_DENOISE_OFFSET1 0x506a
175 #define REG_DENOISE_OFFSET2 0x506b
176 #define REG_SHARPEN_THRESH1 0x506c
177 #define REG_SHARPEN_THRESH2 0x506d
178 #define REG_CIP_CTRL00 0x506e
179 #define REG_CIP_CTRL01 0x506f
181 #define REG_CMX_SIGN 0x5079
182 #define REG_CMX_MISC_CTRL 0x507a
184 #define REG_PRE_ISP_CTRL00 0x50a0
185 #define TEST_PATTERN_ENABLE BIT(7)
186 #define VERTICAL_COLOR_BAR_MASK 0x53
188 #define REG_NULL 0x0000 /* Array end token */
190 #define OV265X_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
191 #define OV2659_ID 0x2656
193 struct sensor_register {
198 struct ov2659_framesize {
202 const struct sensor_register *regs;
205 struct ov2659_pll_ctrl {
211 struct ov2659_pixfmt {
213 /* Output format Register Value (REG_FORMAT_CTRL00) */
214 struct sensor_register *format_ctrl_regs;
217 struct pll_ctrl_reg {
223 struct v4l2_subdev sd;
224 struct media_pad pad;
225 struct v4l2_mbus_framefmt format;
226 unsigned int xvclk_frequency;
227 const struct ov2659_platform_data *pdata;
229 struct i2c_client *client;
230 struct v4l2_ctrl_handler ctrls;
231 struct v4l2_ctrl *link_frequency;
232 const struct ov2659_framesize *frame_size;
233 struct sensor_register *format_ctrl_regs;
234 struct ov2659_pll_ctrl pll;
238 static const struct sensor_register ov2659_init_regs[] = {
239 { REG_IO_CTRL00, 0x03 },
240 { REG_IO_CTRL01, 0xff },
241 { REG_IO_CTRL02, 0xe0 },
249 { REG_TIMING_HS_H, 0x00 },
250 { REG_TIMING_HS_L, 0x00 },
251 { REG_TIMING_VS_H, 0x00 },
252 { REG_TIMING_VS_L, 0x00 },
253 { REG_TIMING_HW_H, 0x06 },
254 { REG_TIMING_HW_L, 0x5f },
255 { REG_TIMING_VH_H, 0x04 },
256 { REG_TIMING_VH_L, 0xb7 },
257 { REG_TIMING_DVPHO_H, 0x03 },
258 { REG_TIMING_DVPHO_L, 0x20 },
259 { REG_TIMING_DVPVO_H, 0x02 },
260 { REG_TIMING_DVPVO_L, 0x58 },
261 { REG_TIMING_HTS_H, 0x05 },
262 { REG_TIMING_HTS_L, 0x14 },
263 { REG_TIMING_VTS_H, 0x02 },
264 { REG_TIMING_VTS_L, 0x68 },
265 { REG_TIMING_HOFFS_L, 0x08 },
266 { REG_TIMING_VOFFS_L, 0x02 },
267 { REG_TIMING_XINC, 0x31 },
268 { REG_TIMING_YINC, 0x31 },
279 { REG_DVP_CTRL02, 0x01 },
287 { REG_TIMING_VERT_FORMAT, 0x81 },
288 { REG_TIMING_HORIZ_FORMAT, 0x01 },
290 { REG_VFIFO_READ_START_H, 0x00 },
291 { REG_VFIFO_READ_START_L, 0x80 },
292 { REG_FORMAT_CTRL00, 0x30 },
294 { REG_ISP_CTRL00, 0xfb },
295 { REG_ISP_CTRL01, 0x1f },
296 { REG_ISP_CTRL02, 0x00 },
322 { REG_CMX_SIGN, 0x98 },
323 { REG_CMX_MISC_CTRL, 0x21 },
324 { REG_AWB_CTRL00, 0x6a },
325 { REG_AWB_CTRL01, 0x11 },
326 { REG_AWB_CTRL02, 0x92 },
327 { REG_AWB_CTRL03, 0x21 },
328 { REG_AWB_CTRL04, 0xe1 },
329 { REG_AWB_LOCAL_LIMIT, 0x01 },
343 { REG_AWB_CTRL12, 0x70 },
344 { REG_AWB_CTRL13, 0xf0 },
345 { REG_AWB_CTRL14, 0xf0 },
346 { REG_LENC_RED_X0_H, 0x03 },
347 { REG_LENC_RED_X0_L, 0x20 },
348 { REG_LENC_RED_Y0_H, 0x02 },
349 { REG_LENC_RED_Y0_L, 0x5c },
350 { REG_LENC_RED_A1, 0x48 },
351 { REG_LENC_RED_B1, 0x00 },
352 { REG_LENC_RED_A2_B2, 0x66 },
353 { REG_LENC_GREEN_X0_H, 0x03 },
354 { REG_LENC_GREEN_X0_L, 0x30 },
355 { REG_LENC_GREEN_Y0_H, 0x02 },
356 { REG_LENC_GREEN_Y0_L, 0x7c },
357 { REG_LENC_GREEN_A1, 0x40 },
358 { REG_LENC_GREEN_B1, 0x00 },
359 { REG_LENC_GREEN_A2_B2, 0x66 },
360 { REG_LENC_BLUE_X0_H, 0x03 },
361 { REG_LENC_BLUE_X0_L, 0x10 },
362 { REG_LENC_BLUE_Y0_H, 0x02 },
363 { REG_LENC_BLUE_Y0_L, 0x7c },
364 { REG_LENC_BLUE_A1, 0x3a },
365 { REG_LENC_BLUE_B1, 0x00 },
366 { REG_LENC_BLUE_A2_B2, 0x66 },
367 { REG_CIP_CTRL00, 0x44 },
368 { REG_SHARPENMT_THRESH1, 0x08 },
369 { REG_SHARPENMT_THRESH2, 0x10 },
370 { REG_SHARPENMT_OFFSET1, 0x12 },
371 { REG_SHARPENMT_OFFSET2, 0x02 },
372 { REG_SHARPEN_THRESH1, 0x08 },
373 { REG_SHARPEN_THRESH2, 0x10 },
374 { REG_CIP_CTRL01, 0xa6 },
375 { REG_DENOISE_THRESH1, 0x08 },
376 { REG_DENOISE_THRESH2, 0x10 },
377 { REG_DENOISE_OFFSET1, 0x04 },
378 { REG_DENOISE_OFFSET2, 0x12 },
382 { REG_CMX_MISC_CTRL, 0x01 },
400 static struct sensor_register ov2659_720p[] = {
401 { REG_TIMING_HS_H, 0x00 },
402 { REG_TIMING_HS_L, 0xa0 },
403 { REG_TIMING_VS_H, 0x00 },
404 { REG_TIMING_VS_L, 0xf0 },
405 { REG_TIMING_HW_H, 0x05 },
406 { REG_TIMING_HW_L, 0xbf },
407 { REG_TIMING_VH_H, 0x03 },
408 { REG_TIMING_VH_L, 0xcb },
409 { REG_TIMING_DVPHO_H, 0x05 },
410 { REG_TIMING_DVPHO_L, 0x00 },
411 { REG_TIMING_DVPVO_H, 0x02 },
412 { REG_TIMING_DVPVO_L, 0xd0 },
413 { REG_TIMING_HTS_H, 0x06 },
414 { REG_TIMING_HTS_L, 0x4c },
415 { REG_TIMING_VTS_H, 0x02 },
416 { REG_TIMING_VTS_L, 0xe8 },
417 { REG_TIMING_HOFFS_L, 0x10 },
418 { REG_TIMING_VOFFS_L, 0x06 },
419 { REG_TIMING_XINC, 0x11 },
420 { REG_TIMING_YINC, 0x11 },
421 { REG_TIMING_VERT_FORMAT, 0x80 },
422 { REG_TIMING_HORIZ_FORMAT, 0x00 },
431 static struct sensor_register ov2659_uxga[] = {
432 { REG_TIMING_HS_H, 0x00 },
433 { REG_TIMING_HS_L, 0x00 },
434 { REG_TIMING_VS_H, 0x00 },
435 { REG_TIMING_VS_L, 0x00 },
436 { REG_TIMING_HW_H, 0x06 },
437 { REG_TIMING_HW_L, 0x5f },
438 { REG_TIMING_VH_H, 0x04 },
439 { REG_TIMING_VH_L, 0xbb },
440 { REG_TIMING_DVPHO_H, 0x06 },
441 { REG_TIMING_DVPHO_L, 0x40 },
442 { REG_TIMING_DVPVO_H, 0x04 },
443 { REG_TIMING_DVPVO_L, 0xb0 },
444 { REG_TIMING_HTS_H, 0x07 },
445 { REG_TIMING_HTS_L, 0x9f },
446 { REG_TIMING_VTS_H, 0x04 },
447 { REG_TIMING_VTS_L, 0xd0 },
448 { REG_TIMING_HOFFS_L, 0x10 },
449 { REG_TIMING_VOFFS_L, 0x06 },
450 { REG_TIMING_XINC, 0x11 },
451 { REG_TIMING_YINC, 0x11 },
469 { REG_TIMING_VERT_FORMAT, 0x80 },
470 { REG_TIMING_HORIZ_FORMAT, 0x00 },
472 { REG_VFIFO_READ_START_H, 0x00 },
473 { REG_VFIFO_READ_START_L, 0x80 },
474 { REG_ISP_CTRL02, 0x00 },
479 static struct sensor_register ov2659_sxga[] = {
480 { REG_TIMING_HS_H, 0x00 },
481 { REG_TIMING_HS_L, 0x00 },
482 { REG_TIMING_VS_H, 0x00 },
483 { REG_TIMING_VS_L, 0x00 },
484 { REG_TIMING_HW_H, 0x06 },
485 { REG_TIMING_HW_L, 0x5f },
486 { REG_TIMING_VH_H, 0x04 },
487 { REG_TIMING_VH_L, 0xb7 },
488 { REG_TIMING_DVPHO_H, 0x05 },
489 { REG_TIMING_DVPHO_L, 0x00 },
490 { REG_TIMING_DVPVO_H, 0x04 },
491 { REG_TIMING_DVPVO_L, 0x00 },
492 { REG_TIMING_HTS_H, 0x07 },
493 { REG_TIMING_HTS_L, 0x9c },
494 { REG_TIMING_VTS_H, 0x04 },
495 { REG_TIMING_VTS_L, 0xd0 },
496 { REG_TIMING_HOFFS_L, 0x10 },
497 { REG_TIMING_VOFFS_L, 0x06 },
498 { REG_TIMING_XINC, 0x11 },
499 { REG_TIMING_YINC, 0x11 },
517 { REG_TIMING_VERT_FORMAT, 0x80 },
518 { REG_TIMING_HORIZ_FORMAT, 0x00 },
520 { REG_VFIFO_READ_START_H, 0x00 },
521 { REG_VFIFO_READ_START_L, 0x80 },
522 { REG_ISP_CTRL02, 0x00 },
527 static struct sensor_register ov2659_xga[] = {
528 { REG_TIMING_HS_H, 0x00 },
529 { REG_TIMING_HS_L, 0x00 },
530 { REG_TIMING_VS_H, 0x00 },
531 { REG_TIMING_VS_L, 0x00 },
532 { REG_TIMING_HW_H, 0x06 },
533 { REG_TIMING_HW_L, 0x5f },
534 { REG_TIMING_VH_H, 0x04 },
535 { REG_TIMING_VH_L, 0xb7 },
536 { REG_TIMING_DVPHO_H, 0x04 },
537 { REG_TIMING_DVPHO_L, 0x00 },
538 { REG_TIMING_DVPVO_H, 0x03 },
539 { REG_TIMING_DVPVO_L, 0x00 },
540 { REG_TIMING_HTS_H, 0x07 },
541 { REG_TIMING_HTS_L, 0x9c },
542 { REG_TIMING_VTS_H, 0x04 },
543 { REG_TIMING_VTS_L, 0xd0 },
544 { REG_TIMING_HOFFS_L, 0x10 },
545 { REG_TIMING_VOFFS_L, 0x06 },
546 { REG_TIMING_XINC, 0x11 },
547 { REG_TIMING_YINC, 0x11 },
565 { REG_TIMING_VERT_FORMAT, 0x80 },
566 { REG_TIMING_HORIZ_FORMAT, 0x00 },
568 { REG_VFIFO_READ_START_H, 0x00 },
569 { REG_VFIFO_READ_START_L, 0x80 },
570 { REG_ISP_CTRL02, 0x00 },
575 static struct sensor_register ov2659_svga[] = {
576 { REG_TIMING_HS_H, 0x00 },
577 { REG_TIMING_HS_L, 0x00 },
578 { REG_TIMING_VS_H, 0x00 },
579 { REG_TIMING_VS_L, 0x00 },
580 { REG_TIMING_HW_H, 0x06 },
581 { REG_TIMING_HW_L, 0x5f },
582 { REG_TIMING_VH_H, 0x04 },
583 { REG_TIMING_VH_L, 0xb7 },
584 { REG_TIMING_DVPHO_H, 0x03 },
585 { REG_TIMING_DVPHO_L, 0x20 },
586 { REG_TIMING_DVPVO_H, 0x02 },
587 { REG_TIMING_DVPVO_L, 0x58 },
588 { REG_TIMING_HTS_H, 0x05 },
589 { REG_TIMING_HTS_L, 0x14 },
590 { REG_TIMING_VTS_H, 0x02 },
591 { REG_TIMING_VTS_L, 0x68 },
592 { REG_TIMING_HOFFS_L, 0x08 },
593 { REG_TIMING_VOFFS_L, 0x02 },
594 { REG_TIMING_XINC, 0x31 },
595 { REG_TIMING_YINC, 0x31 },
613 { REG_TIMING_VERT_FORMAT, 0x81 },
614 { REG_TIMING_HORIZ_FORMAT, 0x01 },
616 { REG_VFIFO_READ_START_H, 0x00 },
617 { REG_VFIFO_READ_START_L, 0x80 },
618 { REG_ISP_CTRL02, 0x00 },
623 static struct sensor_register ov2659_vga[] = {
624 { REG_TIMING_HS_H, 0x00 },
625 { REG_TIMING_HS_L, 0x00 },
626 { REG_TIMING_VS_H, 0x00 },
627 { REG_TIMING_VS_L, 0x00 },
628 { REG_TIMING_HW_H, 0x06 },
629 { REG_TIMING_HW_L, 0x5f },
630 { REG_TIMING_VH_H, 0x04 },
631 { REG_TIMING_VH_L, 0xb7 },
632 { REG_TIMING_DVPHO_H, 0x02 },
633 { REG_TIMING_DVPHO_L, 0x80 },
634 { REG_TIMING_DVPVO_H, 0x01 },
635 { REG_TIMING_DVPVO_L, 0xe0 },
636 { REG_TIMING_HTS_H, 0x05 },
637 { REG_TIMING_HTS_L, 0x14 },
638 { REG_TIMING_VTS_H, 0x02 },
639 { REG_TIMING_VTS_L, 0x68 },
640 { REG_TIMING_HOFFS_L, 0x08 },
641 { REG_TIMING_VOFFS_L, 0x02 },
642 { REG_TIMING_XINC, 0x31 },
643 { REG_TIMING_YINC, 0x31 },
661 { REG_TIMING_VERT_FORMAT, 0x81 },
662 { REG_TIMING_HORIZ_FORMAT, 0x01 },
664 { REG_VFIFO_READ_START_H, 0x00 },
665 { REG_VFIFO_READ_START_L, 0x80 },
666 { REG_ISP_CTRL02, 0x10 },
671 static struct sensor_register ov2659_qvga[] = {
672 { REG_TIMING_HS_H, 0x00 },
673 { REG_TIMING_HS_L, 0x00 },
674 { REG_TIMING_VS_H, 0x00 },
675 { REG_TIMING_VS_L, 0x00 },
676 { REG_TIMING_HW_H, 0x06 },
677 { REG_TIMING_HW_L, 0x5f },
678 { REG_TIMING_VH_H, 0x04 },
679 { REG_TIMING_VH_L, 0xb7 },
680 { REG_TIMING_DVPHO_H, 0x01 },
681 { REG_TIMING_DVPHO_L, 0x40 },
682 { REG_TIMING_DVPVO_H, 0x00 },
683 { REG_TIMING_DVPVO_L, 0xf0 },
684 { REG_TIMING_HTS_H, 0x05 },
685 { REG_TIMING_HTS_L, 0x14 },
686 { REG_TIMING_VTS_H, 0x02 },
687 { REG_TIMING_VTS_L, 0x68 },
688 { REG_TIMING_HOFFS_L, 0x08 },
689 { REG_TIMING_VOFFS_L, 0x02 },
690 { REG_TIMING_XINC, 0x31 },
691 { REG_TIMING_YINC, 0x31 },
709 { REG_TIMING_VERT_FORMAT, 0x81 },
710 { REG_TIMING_HORIZ_FORMAT, 0x01 },
712 { REG_VFIFO_READ_START_H, 0x00 },
713 { REG_VFIFO_READ_START_L, 0x80 },
714 { REG_ISP_CTRL02, 0x10 },
718 static const struct pll_ctrl_reg ctrl3[] = {
735 static const struct pll_ctrl_reg ctrl1[] = {
754 static const struct ov2659_framesize ov2659_framesizes[] = {
759 .max_exp_lines = 248,
764 .max_exp_lines = 498,
769 .max_exp_lines = 498,
774 .max_exp_lines = 498,
779 .max_exp_lines = 498,
784 .max_exp_lines = 1048,
789 .max_exp_lines = 498,
794 static struct sensor_register ov2659_format_yuyv[] = {
795 { REG_FORMAT_CTRL00, 0x30 },
800 static struct sensor_register ov2659_format_uyvy[] = {
801 { REG_FORMAT_CTRL00, 0x32 },
806 static struct sensor_register ov2659_format_bggr[] = {
807 { REG_FORMAT_CTRL00, 0x00 },
812 static struct sensor_register ov2659_format_rgb565[] = {
813 { REG_FORMAT_CTRL00, 0x60 },
817 static const struct ov2659_pixfmt ov2659_formats[] = {
819 .code = MEDIA_BUS_FMT_YUYV8_2X8,
820 .format_ctrl_regs = ov2659_format_yuyv,
822 .code = MEDIA_BUS_FMT_UYVY8_2X8,
823 .format_ctrl_regs = ov2659_format_uyvy,
825 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
826 .format_ctrl_regs = ov2659_format_rgb565,
828 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
829 .format_ctrl_regs = ov2659_format_bggr,
833 static inline struct ov2659 *to_ov2659(struct v4l2_subdev *sd)
835 return container_of(sd, struct ov2659, sd);
838 /* sensor register write */
839 static int ov2659_write(struct i2c_client *client, u16 reg, u8 val)
849 msg.addr = client->addr;
850 msg.flags = client->flags;
852 msg.len = sizeof(buf);
854 ret = i2c_transfer(client->adapter, &msg, 1);
858 dev_dbg(&client->dev,
859 "ov2659 write reg(0x%x val:0x%x) failed !\n", reg, val);
864 /* sensor register read */
865 static int ov2659_read(struct i2c_client *client, u16 reg, u8 *val)
867 struct i2c_msg msg[2];
874 msg[0].addr = client->addr;
875 msg[0].flags = client->flags;
877 msg[0].len = sizeof(buf);
879 msg[1].addr = client->addr;
880 msg[1].flags = client->flags | I2C_M_RD;
884 ret = i2c_transfer(client->adapter, msg, 2);
890 dev_dbg(&client->dev,
891 "ov2659 read reg(0x%x val:0x%x) failed !\n", reg, *val);
896 static int ov2659_write_array(struct i2c_client *client,
897 const struct sensor_register *regs)
901 for (i = 0; ret == 0 && regs[i].addr; i++)
902 ret = ov2659_write(client, regs[i].addr, regs[i].value);
907 static void ov2659_pll_calc_params(struct ov2659 *ov2659)
909 const struct ov2659_platform_data *pdata = ov2659->pdata;
910 u8 ctrl1_reg = 0, ctrl2_reg = 0, ctrl3_reg = 0;
911 struct i2c_client *client = ov2659->client;
912 unsigned int desired = pdata->link_frequency;
913 u32 prediv, postdiv, mult;
918 for (i = 0; ctrl1[i].div != 0; i++) {
919 postdiv = ctrl1[i].div;
920 for (j = 0; ctrl3[j].div != 0; j++) {
921 prediv = ctrl3[j].div;
922 for (mult = 1; mult <= 63; mult++) {
923 actual = ov2659->xvclk_frequency;
927 delta = actual - desired;
930 if ((delta < bestdelta) || (bestdelta == -1)) {
932 ctrl1_reg = ctrl1[i].reg;
934 ctrl3_reg = ctrl3[j].reg;
940 ov2659->pll.ctrl1 = ctrl1_reg;
941 ov2659->pll.ctrl2 = ctrl2_reg;
942 ov2659->pll.ctrl3 = ctrl3_reg;
944 dev_dbg(&client->dev,
945 "Actual reg config: ctrl1_reg: %02x ctrl2_reg: %02x ctrl3_reg: %02x\n",
946 ctrl1_reg, ctrl2_reg, ctrl3_reg);
949 static int ov2659_set_pixel_clock(struct ov2659 *ov2659)
951 struct i2c_client *client = ov2659->client;
952 struct sensor_register pll_regs[] = {
953 {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1},
954 {REG_SC_PLL_CTRL2, ov2659->pll.ctrl2},
955 {REG_SC_PLL_CTRL3, ov2659->pll.ctrl3},
959 dev_dbg(&client->dev, "%s\n", __func__);
961 return ov2659_write_array(client, pll_regs);
964 static void ov2659_get_default_format(struct v4l2_mbus_framefmt *format)
966 format->width = ov2659_framesizes[2].width;
967 format->height = ov2659_framesizes[2].height;
968 format->colorspace = V4L2_COLORSPACE_SRGB;
969 format->code = ov2659_formats[0].code;
970 format->field = V4L2_FIELD_NONE;
973 static void ov2659_set_streaming(struct ov2659 *ov2659, int on)
975 struct i2c_client *client = ov2659->client;
980 dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
982 ret = ov2659_write(client, REG_SOFTWARE_STANDBY, on);
984 dev_err(&client->dev, "ov2659 soft standby failed\n");
987 static int ov2659_init(struct v4l2_subdev *sd, u32 val)
989 struct i2c_client *client = v4l2_get_subdevdata(sd);
991 return ov2659_write_array(client, ov2659_init_regs);
995 * V4L2 subdev video and pad level operations
998 static int ov2659_enum_mbus_code(struct v4l2_subdev *sd,
999 struct v4l2_subdev_pad_config *cfg,
1000 struct v4l2_subdev_mbus_code_enum *code)
1002 struct i2c_client *client = v4l2_get_subdevdata(sd);
1004 dev_dbg(&client->dev, "%s:\n", __func__);
1006 if (code->index >= ARRAY_SIZE(ov2659_formats))
1009 code->code = ov2659_formats[code->index].code;
1014 static int ov2659_enum_frame_sizes(struct v4l2_subdev *sd,
1015 struct v4l2_subdev_pad_config *cfg,
1016 struct v4l2_subdev_frame_size_enum *fse)
1018 struct i2c_client *client = v4l2_get_subdevdata(sd);
1019 int i = ARRAY_SIZE(ov2659_formats);
1021 dev_dbg(&client->dev, "%s:\n", __func__);
1023 if (fse->index >= ARRAY_SIZE(ov2659_framesizes))
1026 speculation_barrier();
1029 if (fse->code == ov2659_formats[i].code)
1032 fse->code = ov2659_formats[i].code;
1034 fse->min_width = ov2659_framesizes[fse->index].width;
1035 fse->max_width = fse->min_width;
1036 fse->max_height = ov2659_framesizes[fse->index].height;
1037 fse->min_height = fse->max_height;
1042 static int ov2659_get_fmt(struct v4l2_subdev *sd,
1043 struct v4l2_subdev_pad_config *cfg,
1044 struct v4l2_subdev_format *fmt)
1046 struct i2c_client *client = v4l2_get_subdevdata(sd);
1047 struct ov2659 *ov2659 = to_ov2659(sd);
1049 dev_dbg(&client->dev, "ov2659_get_fmt\n");
1051 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1052 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1053 struct v4l2_mbus_framefmt *mf;
1055 mf = v4l2_subdev_get_try_format(sd, cfg, 0);
1056 mutex_lock(&ov2659->lock);
1058 mutex_unlock(&ov2659->lock);
1065 mutex_lock(&ov2659->lock);
1066 fmt->format = ov2659->format;
1067 mutex_unlock(&ov2659->lock);
1069 dev_dbg(&client->dev, "ov2659_get_fmt: %x %dx%d\n",
1070 ov2659->format.code, ov2659->format.width,
1071 ov2659->format.height);
1076 static void __ov2659_try_frame_size(struct v4l2_mbus_framefmt *mf,
1077 const struct ov2659_framesize **size)
1079 const struct ov2659_framesize *fsize = &ov2659_framesizes[0];
1080 const struct ov2659_framesize *match = NULL;
1081 int i = ARRAY_SIZE(ov2659_framesizes);
1082 unsigned int min_err = UINT_MAX;
1085 int err = abs(fsize->width - mf->width)
1086 + abs(fsize->height - mf->height);
1087 if ((err < min_err) && (fsize->regs[0].addr)) {
1095 match = &ov2659_framesizes[2];
1097 mf->width = match->width;
1098 mf->height = match->height;
1104 static int ov2659_set_fmt(struct v4l2_subdev *sd,
1105 struct v4l2_subdev_pad_config *cfg,
1106 struct v4l2_subdev_format *fmt)
1108 struct i2c_client *client = v4l2_get_subdevdata(sd);
1109 int index = ARRAY_SIZE(ov2659_formats);
1110 struct v4l2_mbus_framefmt *mf = &fmt->format;
1111 const struct ov2659_framesize *size = NULL;
1112 struct ov2659 *ov2659 = to_ov2659(sd);
1115 dev_dbg(&client->dev, "ov2659_set_fmt\n");
1117 __ov2659_try_frame_size(mf, &size);
1119 while (--index >= 0)
1120 if (ov2659_formats[index].code == mf->code)
1126 mf->colorspace = V4L2_COLORSPACE_SRGB;
1127 mf->code = ov2659_formats[index].code;
1128 mf->field = V4L2_FIELD_NONE;
1130 mutex_lock(&ov2659->lock);
1132 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1133 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1134 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1142 if (ov2659->streaming) {
1143 mutex_unlock(&ov2659->lock);
1147 ov2659->frame_size = size;
1148 ov2659->format = fmt->format;
1149 ov2659->format_ctrl_regs =
1150 ov2659_formats[index].format_ctrl_regs;
1152 if (ov2659->format.code != MEDIA_BUS_FMT_SBGGR8_1X8)
1153 val = ov2659->pdata->link_frequency / 2;
1155 val = ov2659->pdata->link_frequency;
1157 ret = v4l2_ctrl_s_ctrl_int64(ov2659->link_frequency, val);
1159 dev_warn(&client->dev,
1160 "failed to set link_frequency rate (%d)\n",
1164 mutex_unlock(&ov2659->lock);
1168 static int ov2659_set_frame_size(struct ov2659 *ov2659)
1170 struct i2c_client *client = ov2659->client;
1172 dev_dbg(&client->dev, "%s\n", __func__);
1174 return ov2659_write_array(ov2659->client, ov2659->frame_size->regs);
1177 static int ov2659_set_format(struct ov2659 *ov2659)
1179 struct i2c_client *client = ov2659->client;
1181 dev_dbg(&client->dev, "%s\n", __func__);
1183 return ov2659_write_array(ov2659->client, ov2659->format_ctrl_regs);
1186 static int ov2659_s_stream(struct v4l2_subdev *sd, int on)
1188 struct i2c_client *client = v4l2_get_subdevdata(sd);
1189 struct ov2659 *ov2659 = to_ov2659(sd);
1192 dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
1194 mutex_lock(&ov2659->lock);
1198 if (ov2659->streaming == on)
1202 /* Stop Streaming Sequence */
1203 ov2659_set_streaming(ov2659, 0);
1204 ov2659->streaming = on;
1208 ov2659_set_pixel_clock(ov2659);
1209 ov2659_set_frame_size(ov2659);
1210 ov2659_set_format(ov2659);
1211 ov2659_set_streaming(ov2659, 1);
1212 ov2659->streaming = on;
1215 mutex_unlock(&ov2659->lock);
1219 static int ov2659_set_test_pattern(struct ov2659 *ov2659, int value)
1221 struct i2c_client *client = v4l2_get_subdevdata(&ov2659->sd);
1225 ret = ov2659_read(client, REG_PRE_ISP_CTRL00, &val);
1231 val &= ~TEST_PATTERN_ENABLE;
1234 val &= VERTICAL_COLOR_BAR_MASK;
1235 val |= TEST_PATTERN_ENABLE;
1239 return ov2659_write(client, REG_PRE_ISP_CTRL00, val);
1242 static int ov2659_s_ctrl(struct v4l2_ctrl *ctrl)
1244 struct ov2659 *ov2659 =
1245 container_of(ctrl->handler, struct ov2659, ctrls);
1248 case V4L2_CID_TEST_PATTERN:
1249 return ov2659_set_test_pattern(ov2659, ctrl->val);
1255 static struct v4l2_ctrl_ops ov2659_ctrl_ops = {
1256 .s_ctrl = ov2659_s_ctrl,
1259 static const char * const ov2659_test_pattern_menu[] = {
1261 "Vertical Color Bars",
1264 /* -----------------------------------------------------------------------------
1265 * V4L2 subdev internal operations
1268 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1269 static int ov2659_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1271 struct i2c_client *client = v4l2_get_subdevdata(sd);
1272 struct v4l2_mbus_framefmt *format =
1273 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1275 dev_dbg(&client->dev, "%s:\n", __func__);
1277 ov2659_get_default_format(format);
1283 static const struct v4l2_subdev_core_ops ov2659_subdev_core_ops = {
1284 .log_status = v4l2_ctrl_subdev_log_status,
1285 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1286 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1289 static const struct v4l2_subdev_video_ops ov2659_subdev_video_ops = {
1290 .s_stream = ov2659_s_stream,
1293 static const struct v4l2_subdev_pad_ops ov2659_subdev_pad_ops = {
1294 .enum_mbus_code = ov2659_enum_mbus_code,
1295 .enum_frame_size = ov2659_enum_frame_sizes,
1296 .get_fmt = ov2659_get_fmt,
1297 .set_fmt = ov2659_set_fmt,
1300 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1301 static const struct v4l2_subdev_ops ov2659_subdev_ops = {
1302 .core = &ov2659_subdev_core_ops,
1303 .video = &ov2659_subdev_video_ops,
1304 .pad = &ov2659_subdev_pad_ops,
1307 static const struct v4l2_subdev_internal_ops ov2659_subdev_internal_ops = {
1308 .open = ov2659_open,
1312 static int ov2659_detect(struct v4l2_subdev *sd)
1314 struct i2c_client *client = v4l2_get_subdevdata(sd);
1318 dev_dbg(&client->dev, "%s:\n", __func__);
1320 ret = ov2659_write(client, REG_SOFTWARE_RESET, 0x01);
1322 dev_err(&client->dev, "Sensor soft reset failed\n");
1325 usleep_range(1000, 2000);
1327 ret = ov2659_init(sd, 0);
1331 /* Check sensor revision */
1332 ret = ov2659_read(client, REG_SC_CHIP_ID_H, &pid);
1334 ret = ov2659_read(client, REG_SC_CHIP_ID_L, &ver);
1339 id = OV265X_ID(pid, ver);
1340 if (id != OV2659_ID)
1341 dev_err(&client->dev,
1342 "Sensor detection failed (%04X, %d)\n",
1345 dev_info(&client->dev, "Found OV%04X sensor\n", id);
1351 static struct ov2659_platform_data *
1352 ov2659_get_pdata(struct i2c_client *client)
1354 struct ov2659_platform_data *pdata;
1355 struct v4l2_of_endpoint *bus_cfg;
1356 struct device_node *endpoint;
1358 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
1359 return client->dev.platform_data;
1361 endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1365 bus_cfg = v4l2_of_alloc_parse_endpoint(endpoint);
1366 if (IS_ERR(bus_cfg)) {
1371 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1375 if (!bus_cfg->nr_of_link_frequencies) {
1376 dev_err(&client->dev,
1377 "link-frequencies property not found or too many\n");
1382 pdata->link_frequency = bus_cfg->link_frequencies[0];
1385 v4l2_of_free_endpoint(bus_cfg);
1386 of_node_put(endpoint);
1390 static int ov2659_probe(struct i2c_client *client,
1391 const struct i2c_device_id *id)
1393 const struct ov2659_platform_data *pdata = ov2659_get_pdata(client);
1394 struct v4l2_subdev *sd;
1395 struct ov2659 *ov2659;
1400 dev_err(&client->dev, "platform data not specified\n");
1404 ov2659 = devm_kzalloc(&client->dev, sizeof(*ov2659), GFP_KERNEL);
1408 ov2659->pdata = pdata;
1409 ov2659->client = client;
1411 clk = devm_clk_get(&client->dev, "xvclk");
1413 return PTR_ERR(clk);
1415 ov2659->xvclk_frequency = clk_get_rate(clk);
1416 if (ov2659->xvclk_frequency < 6000000 ||
1417 ov2659->xvclk_frequency > 27000000)
1420 v4l2_ctrl_handler_init(&ov2659->ctrls, 2);
1421 ov2659->link_frequency =
1422 v4l2_ctrl_new_std(&ov2659->ctrls, &ov2659_ctrl_ops,
1423 V4L2_CID_PIXEL_RATE,
1424 pdata->link_frequency / 2,
1425 pdata->link_frequency, 1,
1426 pdata->link_frequency);
1427 v4l2_ctrl_new_std_menu_items(&ov2659->ctrls, &ov2659_ctrl_ops,
1428 V4L2_CID_TEST_PATTERN,
1429 ARRAY_SIZE(ov2659_test_pattern_menu) - 1,
1430 0, 0, ov2659_test_pattern_menu);
1431 ov2659->sd.ctrl_handler = &ov2659->ctrls;
1433 if (ov2659->ctrls.error) {
1434 dev_err(&client->dev, "%s: control initialization error %d\n",
1435 __func__, ov2659->ctrls.error);
1436 return ov2659->ctrls.error;
1440 client->flags |= I2C_CLIENT_SCCB;
1441 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1442 v4l2_i2c_subdev_init(sd, client, &ov2659_subdev_ops);
1444 sd->internal_ops = &ov2659_subdev_internal_ops;
1445 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1446 V4L2_SUBDEV_FL_HAS_EVENTS;
1449 #if defined(CONFIG_MEDIA_CONTROLLER)
1450 ov2659->pad.flags = MEDIA_PAD_FL_SOURCE;
1451 sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
1452 ret = media_entity_init(&sd->entity, 1, &ov2659->pad, 0);
1454 v4l2_ctrl_handler_free(&ov2659->ctrls);
1459 mutex_init(&ov2659->lock);
1461 ov2659_get_default_format(&ov2659->format);
1462 ov2659->frame_size = &ov2659_framesizes[2];
1463 ov2659->format_ctrl_regs = ov2659_formats[0].format_ctrl_regs;
1465 ret = ov2659_detect(sd);
1469 /* Calculate the PLL register value needed */
1470 ov2659_pll_calc_params(ov2659);
1472 ret = v4l2_async_register_subdev(&ov2659->sd);
1476 dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name);
1481 v4l2_ctrl_handler_free(&ov2659->ctrls);
1482 #if defined(CONFIG_MEDIA_CONTROLLER)
1483 media_entity_cleanup(&sd->entity);
1485 mutex_destroy(&ov2659->lock);
1489 static int ov2659_remove(struct i2c_client *client)
1491 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1492 struct ov2659 *ov2659 = to_ov2659(sd);
1494 v4l2_ctrl_handler_free(&ov2659->ctrls);
1495 v4l2_async_unregister_subdev(sd);
1496 #if defined(CONFIG_MEDIA_CONTROLLER)
1497 media_entity_cleanup(&sd->entity);
1499 mutex_destroy(&ov2659->lock);
1504 static const struct i2c_device_id ov2659_id[] = {
1508 MODULE_DEVICE_TABLE(i2c, ov2659_id);
1510 #if IS_ENABLED(CONFIG_OF)
1511 static const struct of_device_id ov2659_of_match[] = {
1512 { .compatible = "ovti,ov2659", },
1515 MODULE_DEVICE_TABLE(of, ov2659_of_match);
1518 static struct i2c_driver ov2659_i2c_driver = {
1520 .name = DRIVER_NAME,
1521 .of_match_table = of_match_ptr(ov2659_of_match),
1523 .probe = ov2659_probe,
1524 .remove = ov2659_remove,
1525 .id_table = ov2659_id,
1528 module_i2c_driver(ov2659_i2c_driver);
1530 MODULE_AUTHOR("Benoit Parrot <bparrot@ti.com>");
1531 MODULE_DESCRIPTION("OV2659 CMOS Image Sensor driver");
1532 MODULE_LICENSE("GPL v2");