sja1000: fixes

diff --git a/system/ip/sja1000_1.0/component.xml b/system/ip/sja1000_1.0/component.xml
index e1f6e506ea71f0b9e51df185d20c721a1af635fd..08f7d34f587c67d21ac606075b79872cc196c40b 100644 (file)
--- a/system/ip/sja1000_1.0/component.xml
+++ b/system/ip/sja1000_1.0/component.xml
@@ -307,7 +307,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>a4eeabb5</spirit:value>
+            <spirit:value>1333b6f3</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -322,7 +322,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>a4eeabb5</spirit:value>
+            <spirit:value>1333b6f3</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -785,6 +785,10 @@
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
+      <spirit:file>
+        <spirit:name>hdl/can_bsp_txstream.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
       <spirit:file>
         <spirit:name>hdl/can_register_asyn_syn.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
@@ -865,6 +869,10 @@
         <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
+      <spirit:file>
+        <spirit:name>hdl/can_bsp_txstream.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
       <spirit:file>
         <spirit:name>hdl/can_register_asyn_syn.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
@@ -1002,8 +1010,8 @@
         <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
       </xilinx:taxonomies>
       <xilinx:displayName>sja1000_v1.0</xilinx:displayName>
-      <xilinx:coreRevision>23</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2016-05-12T18:22:23Z</xilinx:coreCreationDateTime>
+      <xilinx:coreRevision>30</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2016-05-31T16:16:02Z</xilinx:coreCreationDateTime>
       <xilinx:tags>
         <xilinx:tag xilinx:name="user.org:user:sja1000:1.0_ARCHIVE_LOCATION">/home/martin/projects/cvut/bakalarka/canbench-sw/system/ip/sja1000_1.0</xilinx:tag>
       </xilinx:tags>
@@ -1012,7 +1020,7 @@
       <xilinx:xilinxVersion>2016.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="fa0dead8"/>
       <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ca22a6c3"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8e0f0801"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d7ed6184"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="82d6ec74"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="6f19481e"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="9242ce5e"/>

diff --git a/system/ip/sja1000_1.0/hdl/can_bsp_txstream.v b/system/ip/sja1000_1.0/hdl/can_bsp_txstream.v
index a7447844bf2d92871a505c33016461ad427710c5..ceb06c0a72f8871df13043e72ce48512e8fc225b 100644 (file)
--- a/system/ip/sja1000_1.0/hdl/can_bsp_txstream.v
+++ b/system/ip/sja1000_1.0/hdl/can_bsp_txstream.v
@@ -73,41 +73,44 @@ assign basic_chain_data_byte        = {4'd9,  4'd8,  4'd7,  4'd6, 4'd5, 4'd4, 4'
 assign extended_chain_data_std_byte = {4'd10, 4'd9,  4'd8,  4'd7, 4'd6, 4'd5, 4'd4, 4'd3};
 assign extended_chain_data_ext_byte = {4'd12, 4'd11, 4'd10, 4'd9, 4'd8, 4'd7, 4'd6, 4'd5};
 
+reg [10*4-1 : 0] chain_data_byte;
+
 `ifdef _
 end
 `endif
 
 always @(*)
 begin
-       if (extended_mode)
-       begin
-               if (tx_is_extended_frame)    // Extended frame
-               begin
-                       chain_byte = extended_chain_ext_byte;
-                       chain_duration = extended_chain_ext_duration;
-               end else begin
-                       chain_byte = {{4{4'h0}}, extended_chain_std_byte};
-                       chain_duration = {{4{4'h0}}, extended_chain_std_duration};
-               end
-       end else begin
-               chain_byte = {{5{4'h0}}, basic_chain_byte};
-               chain_duration = {{5{4'h0}}, basic_chain_duration};
-       end
+       casex ({extended_mode, tx_is_extended_frame})
+               2'b11: chain_byte = extended_chain_ext_byte; // Extended mode, Extended frame
+               2'b10: chain_byte = {{4{4'h0}}, extended_chain_std_byte}; // Extended mode, Standard frame
+               2'b0x: chain_byte = {{5{4'h0}}, basic_chain_byte}; // Basic mode
+       endcase
+       casex ({extended_mode, tx_is_extended_frame})
+               2'b11: chain_duration = extended_chain_ext_duration; // Extended mode, Extended frame
+               2'b10: chain_duration = {{4{4'h0}}, extended_chain_std_duration}; // Extended mode, Standard frame
+               2'b0x: chain_duration = {{5{4'h0}}, basic_chain_duration}; // Basic mode
+       endcase
+       casex ({extended_mode, tx_is_extended_frame})
+               2'b11: chain_data_byte <= extended_chain_data_ext_byte; // Extended mode, Extended Frame
+               2'b10: chain_data_byte <= extended_chain_data_std_byte; // Extended mode, Standard Frame
+               2'b0x: chain_data_byte <= basic_chain_data_byte; // Basic mode
+       endcase
 end
 
 always @(posedge rst or posedge clk)
 begin
        if (rst || rst_tx_pointer)
        begin
-               item_idx <= 0;
-               item_cnt <= 0;
+               item_idx <= 4'h0;
+               item_cnt <= 4'h0;
        end 
        else if (~rx_data & ~rx_crc & ~finish_msg)
        begin
                if (item_cnt >= chain_duration[item_idx])
                begin
                        item_idx <= item_idx + 1'b1;
-                       item_cnt <= 0;
+                       item_cnt <= 4'h0;
                end
                else
                        item_cnt <= item_cnt + 1'b1;
@@ -125,20 +128,6 @@ begin
                tx_data_addr_o <= tx_data_addr_wire;
 end
 
-reg [10*4-1 : 0] chain_data_byte;
-
-always @(*)
-begin
-       if (extended_mode) // Extended mode
-       begin
-               if (tx_is_extended_frame)    // Extended frame
-                       chain_data_byte <= extended_chain_data_ext_byte;
-               else
-                       chain_data_byte <= extended_chain_data_std_byte;
-       end
-       else   // Basic mode
-               chain_data_byte <= basic_chain_data_byte;
-end
 
 
 integer i;
@@ -149,22 +138,15 @@ begin
        if (rx_data)  // data stage
        begin
                case (data_byte_idx)
-                       3'h0: tx_data_addr_wire = chain_data_byte[0*4+3 : 0*4];
-                       3'h1: tx_data_addr_wire = chain_data_byte[1*4+3 : 1*4];
-                       3'h2: tx_data_addr_wire = chain_data_byte[2*4+3 : 2*4];
-                       3'h3: tx_data_addr_wire = chain_data_byte[3*4+3 : 3*4];
-                       3'h4: tx_data_addr_wire = chain_data_byte[4*4+3 : 4*4];
-                       3'h5: tx_data_addr_wire = chain_data_byte[5*4+3 : 5*4];
-                       3'h6: tx_data_addr_wire = chain_data_byte[6*4+3 : 6*4];
-                       3'h7: tx_data_addr_wire = chain_data_byte[7*4+3 : 7*4];
-                       3'h8: tx_data_addr_wire = chain_data_byte[8*4+3 : 8*4];
-                       3'h9: tx_data_addr_wire = chain_data_byte[9*4+3 : 9*4];
-                       3'ha: tx_data_addr_wire = chain_data_byte[10*4+3 : 10*4];
-                       3'hb: tx_data_addr_wire = chain_data_byte[11*4+3 : 11*4];
-                       3'hc: tx_data_addr_wire = chain_data_byte[12*4+3 : 12*4];
-                       3'hd: tx_data_addr_wire = chain_data_byte[13*4+3 : 13*4];
-                       3'he: tx_data_addr_wire = chain_data_byte[14*4+3 : 14*4];
-                       3'hf: tx_data_addr_wire = chain_data_byte[15*4+3 : 15*4];
+                       3'h0: tx_data_addr_wire <= chain_data_byte[0*4+3 : 0*4];
+                       3'h1: tx_data_addr_wire <= chain_data_byte[1*4+3 : 1*4];
+                       3'h2: tx_data_addr_wire <= chain_data_byte[2*4+3 : 2*4];
+                       3'h3: tx_data_addr_wire <= chain_data_byte[3*4+3 : 3*4];
+                       3'h4: tx_data_addr_wire <= chain_data_byte[4*4+3 : 4*4];
+                       3'h5: tx_data_addr_wire <= chain_data_byte[5*4+3 : 5*4];
+                       3'h6: tx_data_addr_wire <= chain_data_byte[6*4+3 : 6*4];
+                       3'h7: tx_data_addr_wire <= chain_data_byte[7*4+3 : 7*4];
+                       default: $error("impossible");
                endcase
                //tx_data_addr_wire = chain_data_byte[data_byte_idx*4+3 +: 4]; 
        end
@@ -174,22 +156,25 @@ begin
                tx_data_addr_wire <= 4'hx;
        else
                case (item_idx)
-                       3'h0: tx_data_addr_wire = chain_byte[0*4+3 : 0*4];
-                       3'h1: tx_data_addr_wire = chain_byte[1*4+3 : 1*4];
-                       3'h2: tx_data_addr_wire = chain_byte[2*4+3 : 2*4];
-                       3'h3: tx_data_addr_wire = chain_byte[3*4+3 : 3*4];
-                       3'h4: tx_data_addr_wire = chain_byte[4*4+3 : 4*4];
-                       3'h5: tx_data_addr_wire = chain_byte[5*4+3 : 5*4];
-                       3'h6: tx_data_addr_wire = chain_byte[6*4+3 : 6*4];
-                       3'h7: tx_data_addr_wire = chain_byte[7*4+3 : 7*4];
-                       3'h8: tx_data_addr_wire = chain_byte[8*4+3 : 8*4];
-                       3'h9: tx_data_addr_wire = chain_byte[9*4+3 : 9*4];
-                       3'ha: tx_data_addr_wire = chain_byte[10*4+3 : 10*4];
-                       3'hb: tx_data_addr_wire = chain_byte[11*4+3 : 11*4];
-                       3'hc: tx_data_addr_wire = chain_byte[12*4+3 : 12*4];
-                       3'hd: tx_data_addr_wire = chain_byte[13*4+3 : 13*4];
-                       3'he: tx_data_addr_wire = chain_byte[14*4+3 : 14*4];
-                       3'hf: tx_data_addr_wire = chain_byte[15*4+3 : 15*4];
+                       4'h0: tx_data_addr_wire <= chain_byte[0*4+3 : 0*4];
+                       4'h1: tx_data_addr_wire <= chain_byte[1*4+3 : 1*4];
+                       4'h2: tx_data_addr_wire <= chain_byte[2*4+3 : 2*4];
+                       4'h3: tx_data_addr_wire <= chain_byte[3*4+3 : 3*4];
+                       4'h4: tx_data_addr_wire <= chain_byte[4*4+3 : 4*4];
+                       4'h5: tx_data_addr_wire <= chain_byte[5*4+3 : 5*4];
+                       4'h6: tx_data_addr_wire <= chain_byte[6*4+3 : 6*4];
+                       4'h7: tx_data_addr_wire <= chain_byte[7*4+3 : 7*4];
+                       4'h8: tx_data_addr_wire <= chain_byte[8*4+3 : 8*4];
+                       4'h9: tx_data_addr_wire <= chain_byte[9*4+3 : 9*4];
+                       default: tx_data_addr_wire <= 4'hx;
+                       /*
+                       4'ha: tx_data_addr_wire <= chain_byte[10*4+3 : 10*4];
+                       4'hb: tx_data_addr_wire <= chain_byte[11*4+3 : 11*4];
+                       4'hc: tx_data_addr_wire <= chain_byte[12*4+3 : 12*4];
+                       4'hd: tx_data_addr_wire <= chain_byte[13*4+3 : 13*4];
+                       4'he: tx_data_addr_wire <= chain_byte[14*4+3 : 14*4];
+                       4'hf: tx_data_addr_wire <= chain_byte[15*4+3 : 15*4];
+                       */
                endcase
                //tx_data_addr_wire <= 4'hx;//chain_byte[item_idx]; // TODO
 end