]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commit
xilinx_can: fixed HW timestamping (fuzzy overflow checking)
authorMartin Jerabek <jerabma7@fel.cvut.cz>
Wed, 18 May 2016 23:00:41 +0000 (01:00 +0200)
committerMartin Jerabek <jerabma7@fel.cvut.cz>
Wed, 18 May 2016 23:01:50 +0000 (01:01 +0200)
commit8db1826d5e55a3e0ffa06bfbdaf7fa1f3e108ef1
treed0ff678bb2ebbccf0afd9726cdc7c857f4143e71
parent281c87172ed5eadcd6b8deb66b3313832816a174
xilinx_can: fixed HW timestamping (fuzzy overflow checking)
petalinux/components/modules/xilinx_can/xilinx_can.c