<spirit:parameters>
<spirit:parameter>
<spirit:name>WIZ_DATA_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_ea018de4">32</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>WIZ_NUM_REG</spirit:name>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>IRQ</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>INTERRUPT</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>irq</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>SENSITIVITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.IRQ.SENSITIVITY">LEVEL_HIGH</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>S_AXI_INTR</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
- <spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_INTR"/>
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- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWADDR</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>s_axi_intr_awaddr</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWPROT</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>s_axi_intr_awprot</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>s_axi_intr_awvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>s_axi_intr_awready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WDATA</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_wdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WSTRB</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_wstrb</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_wvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>s_axi_intr_wready</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BRESP</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_bresp</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_bvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BREADY</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_bready</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARADDR</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_araddr</spirit:name>
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- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARPROT</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_arprot</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_arvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>s_axi_intr_arready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>s_axi_intr_rdata</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RRESP</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_rresp</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_rvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RREADY</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>s_axi_intr_rready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
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- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>WIZ_DATA_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_INTR.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_ea018de4">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>WIZ_NUM_REG</spirit:name>
- <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_INTR.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">5</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
- <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_INTR.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
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- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>S_AXI_INTR_RST</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>s_axi_intr_aresetn</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_INTR_RST.POLARITY">ACTIVE_LOW</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>S_AXI_INTR_CLK</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>s_axi_intr_aclk</spirit:name>
- </spirit:physicalPort>
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- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_BUSIF</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_INTR_CLK.ASSOCIATED_BUSIF">S_AXI_INTR</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_INTR_CLK.ASSOCIATED_RESET">s_axi_intr_aresetn</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
<spirit:busInterface>
<spirit:name>S00_AXI_RST</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:memoryMaps>
- <spirit:memoryMap>
- <spirit:name>S_AXI_INTR</spirit:name>
- <spirit:addressBlock>
- <spirit:name>S_AXI_INTR_reg</spirit:name>
- <spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
- <spirit:range spirit:format="long">4096</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>OFFSET_BASE_PARAM</spirit:name>
- <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_INTR.S_AXI_INTR_REG.OFFSET_BASE_PARAM" spirit:dependency="ADDRBLOCKPARAM_VALUE.S_AXI_INTR_reg.OFFSET_BASE_PARAM">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
- <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_INTR.S_AXI_INTR_REG.OFFSET_HIGH_PARAM" spirit:dependency="ADDRBLOCKPARAM_VALUE.S_AXI_INTR_reg.OFFSET_HIGH_PARAM">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:addressBlock>
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<spirit:memoryMap>
<spirit:name>S00_AXI</spirit:name>
<spirit:addressBlock>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
- <spirit:view>
- <spirit:name>xilinx_vhdlsynthesis</spirit:name>
- <spirit:displayName>VHDL Synthesis</spirit:displayName>
- <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
- <spirit:language>vhdl</spirit:language>
- <spirit:modelName>sja1000_v1_0</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
- </spirit:fileSetRef>
- </spirit:view>
- <spirit:view>
- <spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
- <spirit:displayName>VHDL Simulation</spirit:displayName>
- <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
- <spirit:language>vhdl</spirit:language>
- <spirit:modelName>sja1000_v1_0</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
- </spirit:fileSetRef>
- </spirit:view>
<spirit:view>
<spirit:name>xilinx_softwaredriver</spirit:name>
<spirit:displayName>Software Driver</spirit:displayName>
<spirit:fileSetRef>
<spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
</spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>a7e67acd</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
</spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>fd592ead</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>bd_tcl</spirit:name>
<spirit:fileSetRef>
<spirit:localName>bd_tcl_view_fileset</spirit:localName>
</spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>45a2f450</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+ <spirit:displayName>Synthesis</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:modelName>sja1000</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>4030548c</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:modelName>sja1000</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>4030548c</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
- <spirit:name>s_axi_intr_awaddr</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH'))-1)">4</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
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- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_intr_awprot</spirit:name>
- <spirit:wire>
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- <spirit:left spirit:format="long">2</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
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- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
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- </spirit:wire>
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- <spirit:port>
- <spirit:name>s_axi_intr_awvalid</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
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- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_intr_awready</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_intr_wdata</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH'))-1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_intr_wstrb</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH'))/8)-1)">3</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
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- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
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- <spirit:port>
- <spirit:name>s_axi_intr_wvalid</spirit:name>
- <spirit:wire>
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- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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- </spirit:wire>
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- <spirit:port>
- <spirit:name>s_axi_intr_wready</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
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- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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- </spirit:wireTypeDef>
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- </spirit:wire>
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- <spirit:port>
- <spirit:name>s_axi_intr_bresp</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
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- <spirit:left spirit:format="long">1</spirit:left>
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- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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- <spirit:port>
- <spirit:name>s_axi_intr_bvalid</spirit:name>
- <spirit:wire>
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- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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- <spirit:name>s_axi_intr_bready</spirit:name>
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- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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- <spirit:port>
- <spirit:name>s_axi_intr_araddr</spirit:name>
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- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH'))-1)">4</spirit:left>
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- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_intr_arprot</spirit:name>
+ <spirit:name>can_clk</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long">2</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
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<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>s_axi_intr_arvalid</spirit:name>
+ <spirit:name>can_rx</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_intr_arready</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_intr_rdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH'))-1)">31</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_intr_rresp</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long">1</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>s_axi_intr_rvalid</spirit:name>
+ <spirit:name>can_tx</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_intr_rready</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_intr_aclk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_intr_aresetn</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>irq</spirit:name>
+ <spirit:name>bus_off_on</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH'))-1)">9</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH'))-1)">31</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH'))/8)-1)">3</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) / 8) - 1)">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH'))-1)">9</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH'))-1)">31</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>irq</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
- <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
- <spirit:name>C_S_AXI_INTR_DATA_WIDTH</spirit:name>
- <spirit:displayName>C S AXI INTR DATA WIDTH</spirit:displayName>
- <spirit:description>Width of S_AXI data bus</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH" spirit:order="3" spirit:rangeType="long">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>C_S_AXI_INTR_ADDR_WIDTH</spirit:name>
- <spirit:displayName>C S AXI INTR ADDR WIDTH</spirit:displayName>
- <spirit:description>Width of S_AXI address bus</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">5</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>C_NUM_OF_INTR</spirit:name>
- <spirit:displayName>C NUM OF INTR</spirit:displayName>
- <spirit:description>Number of Interrupts</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_OF_INTR" spirit:order="5" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="std_logic_vector">
- <spirit:name>C_INTR_SENSITIVITY</spirit:name>
- <spirit:displayName>C INTR SENSITIVITY</spirit:displayName>
- <spirit:description>Each bit corresponds to Sensitivity of interrupt : 0 - EDGE, 1 - LEVEL</spirit:description>
- <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTR_SENSITIVITY" spirit:order="6" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="std_logic_vector">
- <spirit:name>C_INTR_ACTIVE_STATE</spirit:name>
- <spirit:displayName>C INTR ACTIVE STATE</spirit:displayName>
- <spirit:description>Each bit corresponds to Sub-type of INTR: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_INTR_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_INTR_SENSITIVITY is LEVEL(1) ]</spirit:description>
- <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTR_ACTIVE_STATE" spirit:order="7" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>C_IRQ_SENSITIVITY</spirit:name>
- <spirit:displayName>C IRQ SENSITIVITY</spirit:displayName>
- <spirit:description>Sensitivity of IRQ: 0 - EDGE, 1 - LEVEL</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IRQ_SENSITIVITY" spirit:order="8" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
- <spirit:name>C_IRQ_ACTIVE_STATE</spirit:name>
- <spirit:displayName>C IRQ ACTIVE STATE</spirit:displayName>
- <spirit:description>Sub-type of IRQ: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_IRQ_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_IRQ_SENSITIVITY is LEVEL(1) ]</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IRQ_ACTIVE_STATE" spirit:order="9" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI data bus</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="12" spirit:rangeType="long">32</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="3" spirit:rangeType="long">32</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI address bus</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="13" spirit:rangeType="long">10</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">8</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
<spirit:choice>
- <spirit:name>choice_list_ea018de4</spirit:name>
+ <spirit:name>choice_list_6fc15197</spirit:name>
<spirit:enumeration>32</spirit:enumeration>
</spirit:choice>
<spirit:choice>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
- <spirit:file>
- <spirit:name>hdl/sja1000_v1_0_S00_AXI.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdl/sja1000_v1_0_S_AXI_INTR.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
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- <spirit:file>
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- <spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
<spirit:file>
<spirit:file>
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<spirit:fileType>tclSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_9907a0a4</spirit:userFileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileType>tclSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
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+ <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>hdl/can_crc.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+ <spirit:name>hdl/can_fifo.v</spirit:name>
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+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/timescale.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+ <spirit:name>hdl/can_bsp.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+ <spirit:name>hdl/can_registers.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+ <spirit:name>hdl/can_register_asyn.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/sja1000.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+ <spirit:file>
+ <spirit:name>hdl/can_top_raw.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+ <spirit:name>hdl/can_acf.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_ifc_axi.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_register.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_afda1032</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>hdl/can_crc.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_register_asyn_syn.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_fifo.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+ <spirit:file>
+ <spirit:name>hdl/can_register_syn.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_defines.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_btl.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/timescale.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_bsp.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_registers.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_register_asyn.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/sja1000.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_top_raw.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_ibo.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_acf.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_ifc_axi.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_register.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
</spirit:fileSets>
<spirit:description>SJA1000 Soft Core</spirit:description>
<spirit:parameters>
- <spirit:parameter>
- <spirit:name>C_S_AXI_INTR_DATA_WIDTH</spirit:name>
- <spirit:displayName>C S AXI INTR DATA WIDTH</spirit:displayName>
- <spirit:description>Width of S_AXI data bus</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH" spirit:choiceRef="choice_list_ea018de4" spirit:order="3">32</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S_AXI_INTR_DATA_WIDTH">false</xilinx:isEnabled>
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- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_S_AXI_INTR_ADDR_WIDTH</spirit:name>
- <spirit:displayName>C S AXI INTR ADDR WIDTH</spirit:displayName>
- <spirit:description>Width of S_AXI address bus</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">5</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S_AXI_INTR_ADDR_WIDTH">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_NUM_OF_INTR</spirit:name>
- <spirit:displayName>C NUM OF INTR</spirit:displayName>
- <spirit:description>Number of Interrupts</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_OF_INTR" spirit:order="5" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_INTR_SENSITIVITY</spirit:name>
- <spirit:displayName>C INTR SENSITIVITY</spirit:displayName>
- <spirit:description>Each bit corresponds to Sensitivity of interrupt : 0 - EDGE, 1 - LEVEL</spirit:description>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTR_SENSITIVITY" spirit:order="6" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_INTR_ACTIVE_STATE</spirit:name>
- <spirit:displayName>C INTR ACTIVE STATE</spirit:displayName>
- <spirit:description>Each bit corresponds to Sub-type of INTR: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_INTR_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_INTR_SENSITIVITY is LEVEL(1) ]</spirit:description>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTR_ACTIVE_STATE" spirit:order="7" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_IRQ_SENSITIVITY</spirit:name>
- <spirit:displayName>C IRQ SENSITIVITY</spirit:displayName>
- <spirit:description>Sensitivity of IRQ: 0 - EDGE, 1 - LEVEL</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IRQ_SENSITIVITY" spirit:order="8" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_IRQ_ACTIVE_STATE</spirit:name>
- <spirit:displayName>C IRQ ACTIVE STATE</spirit:displayName>
- <spirit:description>Sub-type of IRQ: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_IRQ_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_IRQ_SENSITIVITY is LEVEL(1) ]</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_IRQ_ACTIVE_STATE" spirit:order="9" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_S_AXI_INTR_BASEADDR</spirit:name>
- <spirit:displayName>C S AXI INTR BASEADDR</spirit:displayName>
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- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S_AXI_INTR_BASEADDR">false</xilinx:isEnabled>
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- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_S_AXI_INTR_HIGHADDR</spirit:name>
- <spirit:displayName>C S AXI INTR HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_INTR_HIGHADDR" spirit:order="11" spirit:bitStringLength="32">0x00000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S_AXI_INTR_HIGHADDR">false</xilinx:isEnabled>
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- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
<spirit:parameter>
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI data bus</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_ea018de4" spirit:order="12">32</spirit:value>
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<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
<spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
<spirit:description>Width of S_AXI address bus</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="13" spirit:rangeType="long">10</spirit:value>
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<xilinx:enablement>
<spirit:parameter>
<spirit:name>C_S00_AXI_BASEADDR</spirit:name>
<spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
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- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
<spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="15" spirit:bitStringLength="32">0x00000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>sja1000_v1.0</xilinx:displayName>
- <xilinx:coreRevision>1</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2016-05-08T23:03:05Z</xilinx:coreCreationDateTime>
+ <xilinx:coreRevision>3</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2016-05-11T10:03:38Z</xilinx:coreCreationDateTime>
+ <xilinx:tags>
+ <xilinx:tag xilinx:name="user.org:user:sja1000:1.0_ARCHIVE_LOCATION">/home/martin/projects/cvut/bakalarka/canbench-sw/system/ip/sja1000_1.0</xilinx:tag>
+ </xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2015.4</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="5dbb9758"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ca22a6c3"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0b6c5764"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="2af143f4"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8a3bfb41"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="edbec00a"/>
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