+ component cnt_div is
+ generic (
+ cnt_width_g : natural := 4
+ );
+ port
+ (
+ clk_i : in std_logic; --clk to divide
+ en_i : in std_logic; --enable bit?
+ reset_i : in std_logic; --asynch. reset
+ ratio_i : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
+ q_out_o : out std_logic --generates puls when counter underflows
+ );
+ end component;
+
+ component pulse_gen is
+ generic (
+ duration_width_g : natural := 4
+ );
+ port (
+ clk_i : in std_logic; --clk to divide
+ en_i : in std_logic; --enable bit?
+ reset_i : in std_logic; --asynch. reset
+ trigger_i : in std_logic; --start to generate pulse
+ duration_i : in std_logic_vector(duration_width_g-1 downto 0);--duration/interval of the pulse
+ q_out_o : out std_logic --generates pulse for given duration
+ );
+ end component;
+
+ constant audio_pwm_width : integer := 24;
+
+ signal audio_pwm_period: std_logic_vector(audio_pwm_width-1 downto 0);
+ signal audio_pwm_duty: std_logic_vector(audio_pwm_width-1 downto 0);
+
+ signal fsm_clk : std_logic;
+ signal fsm_rst : std_logic;
+
+ signal pwm_cycle_start : std_logic;
+