1 //////////////////////////////////////////////////////////////////////
3 //// can_defines.v ////
6 //// This file is part of the CAN Protocol Controller ////
7 //// http://www.opencores.org/projects/can/ ////
12 //// igorm@opencores.org ////
15 //// All additional information is available in the README.txt ////
18 //////////////////////////////////////////////////////////////////////
20 //// Copyright (C) 2002, 2003, 2004 Authors ////
22 //// This source file may be used and distributed without ////
23 //// restriction provided that this copyright statement is not ////
24 //// removed from the file and that any derivative work contains ////
25 //// the original copyright notice and the associated disclaimer. ////
27 //// This source file is free software; you can redistribute it ////
28 //// and/or modify it under the terms of the GNU Lesser General ////
29 //// Public License as published by the Free Software Foundation; ////
30 //// either version 2.1 of the License, or (at your option) any ////
31 //// later version. ////
33 //// This source is distributed in the hope that it will be ////
34 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
35 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
36 //// PURPOSE. See the GNU Lesser General Public License for more ////
39 //// You should have received a copy of the GNU Lesser General ////
40 //// Public License along with this source; if not, download it ////
41 //// from http://www.opencores.org/lgpl.shtml ////
43 //// The CAN protocol is developed by Robert Bosch GmbH and ////
44 //// protected by patents. Anybody who wants to implement this ////
45 //// CAN IP core on silicon has to obtain a CAN protocol license ////
48 //////////////////////////////////////////////////////////////////////
50 // CVS Revision History
52 // $Log: not supported by cvs2svn $
53 // Revision 1.13 2004/02/08 14:28:03 mohor
56 // Revision 1.12 2003/10/17 05:55:20 markom
57 // mbist signals updated according to newest convention
59 // Revision 1.11 2003/09/05 12:46:42 mohor
60 // ALTERA_RAM supported.
62 // Revision 1.10 2003/08/14 16:04:52 simons
63 // Artisan ram instances added.
65 // Revision 1.9 2003/06/27 20:56:15 simons
66 // Virtual silicon ram instances added.
68 // Revision 1.8 2003/06/09 11:32:36 mohor
69 // Ports added for the CAN_BIST.
71 // Revision 1.7 2003/03/20 16:51:55 mohor
72 // *** empty log message ***
74 // Revision 1.6 2003/03/12 04:19:13 mohor
75 // 8051 interface added (besides WISHBONE interface). Selection is made in
76 // can_defines.v file.
78 // Revision 1.5 2003/03/05 15:03:20 mohor
81 // Revision 1.4 2003/03/01 22:52:47 mohor
82 // Actel APA ram supported.
84 // Revision 1.3 2003/02/09 02:24:33 mohor
85 // Bosch license warning added. Error counters finished. Overload frames
86 // still need to be fixed.
88 // Revision 1.2 2002/12/27 00:12:52 mohor
89 // Header changed, testbench improved to send a frame (crc still missing).
91 // Revision 1.1.1.1 2002/12/20 16:39:21 mohor
98 // Uncomment following line if you want to use WISHBONE interface. Otherwise
99 // 8051 interface is used.
100 `define CAN_WISHBONE_IF
102 // Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)
103 // `define ACTEL_APA_RAM
105 // Uncomment following line if you want to use CAN in Altera devices (embedded memory used)
106 // `define ALTERA_RAM
108 // Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
109 // `define XILINX_RAM
111 // Uncomment the line for the ram used in ASIC implementation
112 // `define VIRTUALSILICON_RAM
113 // `define ARTISAN_RAM
115 // Uncomment the following line when RAM BIST is needed (ASIC implementation)
116 //`define CAN_BIST // Bist (for ASIC implementation)
118 /* width of MBIST control bus */
119 //`define CAN_MBIST_CTRL_WIDTH 3