system/ip/spi_leds_and_enc_1.0/hdl/spi_leds_and_enc_v1_0.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 entity spi_leds_and_enc_v1_0 is
   6         generic (
   7                 -- Users to add parameters here
   8
   9                 -- User parameters ends
  10                 -- Do not modify the parameters beyond this line
  11
  12
  13                 -- Parameters of Axi Slave Bus Interface S00_AXI
  14                 C_S00_AXI_DATA_WIDTH    : integer       := 32;
  15                 C_S00_AXI_ADDR_WIDTH    : integer       := 6
  16         );
  17         port (
  18                 -- Users to add ports here
  19                 spi_led_reset   : out std_logic;
  20                 spi_led_clk     : out std_logic;
  21                 spi_led_cs      : out std_logic;
  22                 spi_led_data    : out std_logic;
  23                 spi_led_encin   : in std_logic;
  24                 -- User ports ends
  25                 -- Do not modify the ports beyond this line
  26
  27
  28                 -- Ports of Axi Slave Bus Interface S00_AXI
  29                 s00_axi_aclk    : in std_logic;
  30                 s00_axi_aresetn : in std_logic;
  31                 s00_axi_awaddr  : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
  32                 s00_axi_awprot  : in std_logic_vector(2 downto 0);
  33                 s00_axi_awvalid : in std_logic;
  34                 s00_axi_awready : out std_logic;
  35                 s00_axi_wdata   : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
  36                 s00_axi_wstrb   : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
  37                 s00_axi_wvalid  : in std_logic;
  38                 s00_axi_wready  : out std_logic;
  39                 s00_axi_bresp   : out std_logic_vector(1 downto 0);
  40                 s00_axi_bvalid  : out std_logic;
  41                 s00_axi_bready  : in std_logic;
  42                 s00_axi_araddr  : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
  43                 s00_axi_arprot  : in std_logic_vector(2 downto 0);
  44                 s00_axi_arvalid : in std_logic;
  45                 s00_axi_arready : out std_logic;
  46                 s00_axi_rdata   : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
  47                 s00_axi_rresp   : out std_logic_vector(1 downto 0);
  48                 s00_axi_rvalid  : out std_logic;
  49                 s00_axi_rready  : in std_logic
  50         );
  51 end spi_leds_and_enc_v1_0;
  52
  53 architecture arch_imp of spi_leds_and_enc_v1_0 is
  54
  55         -- component declaration
  56         component spi_leds_and_enc_v1_0_S00_AXI is
  57                 generic (
  58                 C_S_AXI_DATA_WIDTH      : integer       := 32;
  59                 C_S_AXI_ADDR_WIDTH      : integer       := 6
  60                 );
  61                 port (
  62                 S_AXI_ACLK      : in std_logic;
  63                 S_AXI_ARESETN   : in std_logic;
  64                 S_AXI_AWADDR    : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  65                 S_AXI_AWPROT    : in std_logic_vector(2 downto 0);
  66                 S_AXI_AWVALID   : in std_logic;
  67                 S_AXI_AWREADY   : out std_logic;
  68                 S_AXI_WDATA     : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  69                 S_AXI_WSTRB     : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
  70                 S_AXI_WVALID    : in std_logic;
  71                 S_AXI_WREADY    : out std_logic;
  72                 S_AXI_BRESP     : out std_logic_vector(1 downto 0);
  73                 S_AXI_BVALID    : out std_logic;
  74                 S_AXI_BREADY    : in std_logic;
  75                 S_AXI_ARADDR    : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  76                 S_AXI_ARPROT    : in std_logic_vector(2 downto 0);
  77                 S_AXI_ARVALID   : in std_logic;
  78                 S_AXI_ARREADY   : out std_logic;
  79                 S_AXI_RDATA     : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  80                 S_AXI_RRESP     : out std_logic_vector(1 downto 0);
  81                 S_AXI_RVALID    : out std_logic;
  82                 S_AXI_RREADY    : in std_logic
  83                 );
  84         end component spi_leds_and_enc_v1_0_S00_AXI;
  85
  86 begin
  87
  88 -- Instantiation of Axi Bus Interface S00_AXI
  89 spi_leds_and_enc_v1_0_S00_AXI_inst : spi_leds_and_enc_v1_0_S00_AXI
  90         generic map (
  91                 C_S_AXI_DATA_WIDTH      => C_S00_AXI_DATA_WIDTH,
  92                 C_S_AXI_ADDR_WIDTH      => C_S00_AXI_ADDR_WIDTH
  93         )
  94         port map (
  95                 S_AXI_ACLK      => s00_axi_aclk,
  96                 S_AXI_ARESETN   => s00_axi_aresetn,
  97                 S_AXI_AWADDR    => s00_axi_awaddr,
  98                 S_AXI_AWPROT    => s00_axi_awprot,
  99                 S_AXI_AWVALID   => s00_axi_awvalid,
 100                 S_AXI_AWREADY   => s00_axi_awready,
 101                 S_AXI_WDATA     => s00_axi_wdata,
 102                 S_AXI_WSTRB     => s00_axi_wstrb,
 103                 S_AXI_WVALID    => s00_axi_wvalid,
 104                 S_AXI_WREADY    => s00_axi_wready,
 105                 S_AXI_BRESP     => s00_axi_bresp,
 106                 S_AXI_BVALID    => s00_axi_bvalid,
 107                 S_AXI_BREADY    => s00_axi_bready,
 108                 S_AXI_ARADDR    => s00_axi_araddr,
 109                 S_AXI_ARPROT    => s00_axi_arprot,
 110                 S_AXI_ARVALID   => s00_axi_arvalid,
 111                 S_AXI_ARREADY   => s00_axi_arready,
 112                 S_AXI_RDATA     => s00_axi_rdata,
 113                 S_AXI_RRESP     => s00_axi_rresp,
 114                 S_AXI_RVALID    => s00_axi_rvalid,
 115                 S_AXI_RREADY    => s00_axi_rready
 116         );
 117
 118         -- Add user logic here
 119
 120         -- User logic ends
 121
 122 end arch_imp;