system/ip/spi_leds_and_enc_1.0/example_designs/debug_hw_design/design.tcl

   1
   2 proc create_ipi_design { offsetfile design_name } {
   3
   4         create_bd_design $design_name
   5         open_bd_design $design_name
   6
   7         # Create and configure Clock/Reset
   8         create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
   9         create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
  10
  11         #check if current_board is set, if true - figure out required clocks.
  12         set is_board_clock_found 0
  13         set is_board_reset_found 0
  14         set external_reset_port ""
  15         set external_clock_port ""
  16
  17         if { [current_board_part -quiet] != "" } {
  18
  19                 #check if any reset interface exists in board.
  20                 set board_reset [lindex [get_board_part_interfaces -filter { BUSDEF_NAME == reset_rtl && MODE == slave }] 0 ]
  21                 if { $board_reset ne "" } {
  22                         set is_board_reset_found 1
  23                         apply_board_connection -board_interface $board_reset -ip_intf sys_clk_0/reset -diagram [current_bd_design]
  24                         apply_board_connection -board_interface $board_reset -ip_intf sys_reset_0/ext_reset -diagram [current_bd_design]
  25                         set external_rst [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/reset]]]
  26                         if { $external_rst ne "" } {
  27                                 set external_reset_port [get_property NAME $external_rst]
  28                         }
  29                 } else {
  30                         send_msg "ptgen 51-200" WARNING "No reset interface found in current_board, Users may need to specify the location constraints manually."
  31                 }
  32
  33                 # check for differential clock, exclude any special clocks which has TYPE property.
  34                 set board_clock_busifs ""
  35                 foreach busif [get_board_part_interfaces -filter "BUSDEF_NAME == diff_clock_rtl"] {
  36                         set type [get_property PARAM.TYPE $busif]
  37                         if { $type == "" } {
  38                                 set board_clock_busifs $busif
  39                                 break
  40                         }
  41                 }
  42                 if { $board_clock_busifs ne "" } {
  43                         apply_board_connection -board_interface $board_clock_busifs -ip_intf sys_clk_0/CLK_IN1_D -diagram [current_bd_design]
  44                         set is_board_clock_found 1
  45                 } else {
  46                         # check for single ended clock
  47                         set board_sclock_busifs [lindex [get_board_part_interfaces -filter "BUSDEF_NAME == clock_rtl"] 0 ]
  48                         if { $board_sclock_busifs ne "" } {
  49                             apply_board_connection -board_interface $board_sclock_busifs -ip_intf sys_clk_0/clock_CLK_IN1 -diagram [current_bd_design]
  50                                 set external_clk [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/clk_in1]]]
  51                                 if { $external_clk ne "" } {
  52                                         set external_clock_port [get_property NAME $external_clk]
  53                                 }
  54                                 set is_board_clock_found 1
  55                         } else {
  56                                 send_msg "ptgen 51-200" WARNING "No clock interface found in current_board, Users may need to specify the location constraints manually."
  57                         }
  58                 }
  59
  60         } else {
  61                 send_msg "ptgen 51-201" WARNING "No board selected in current_project. Users may need to specify the location constraints manually."
  62         }
  63
  64         #if there is no corresponding board interface found, assume constraints will be provided manually while pin planning.
  65         if { $is_board_reset_found == 0 } {
  66                 create_bd_port -dir I -type rst reset_rtl
  67                 set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
  68                 connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
  69                 connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
  70                 set external_reset_port reset_rtl
  71         }
  72         if { $is_board_clock_found == 0 } {
  73                 create_bd_port -dir I -type clk clock_rtl
  74                 connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
  75                 set external_clock_port clock_rtl
  76         }
  77
  78         #Avoid IPI DRC, make clock port synchronous to reset
  79         if { $external_clock_port ne "" && $external_reset_port ne "" } {
  80                 set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
  81         }
  82
  83         # Connect other sys_reset pins
  84         connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
  85         connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
  86
  87         # Create instance: spi_leds_and_enc_0, and set properties
  88         set spi_leds_and_enc_0 [ create_bd_cell -type ip -vlnv user.org:user:spi_leds_and_enc:1.0 spi_leds_and_enc_0 ]
  89
  90         # Create instance: jtag_axi_0, and set properties
  91         set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
  92         set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
  93         connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
  94         connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
  95
  96         # Create instance: axi_peri_interconnect, and set properties
  97         set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
  98         connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
  99         connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
 100         set_property -dict [ list CONFIG.NUM_SI {1}  ] $axi_peri_interconnect
 101         connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
 102         connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
 103         connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
 104
 105         set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
 106         connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
 107         connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
 108
 109         # Connect all clock & reset of spi_leds_and_enc_0 slave interfaces..
 110         connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins spi_leds_and_enc_0/S00_AXI]
 111         connect_bd_net [get_bd_pins spi_leds_and_enc_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
 112         connect_bd_net [get_bd_pins spi_leds_and_enc_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
 113
 114
 115         # Auto assign address
 116         assign_bd_address
 117
 118         # Copy all address to spi_leds_and_enc_v1_0_include.tcl file
 119         set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
 120         upvar 1 $offsetfile offset_file
 121         set offset_file "${bd_path}/spi_leds_and_enc_v1_0_include.tcl"
 122         set fp [open $offset_file "w"]
 123         puts $fp "# Configuration address parameters"
 124
 125         set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_spi_leds_and_enc_0_S00_AXI_* ]]
 126         puts $fp "set s00_axi_addr ${offset}"
 127
 128         close $fp
 129 }
 130
 131 # Set IP Repository and Update IP Catalogue
 132 set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:spi_leds_and_enc:1.0]]]]
 133 set hw_test_file ${ip_path}/example_designs/debug_hw_design/spi_leds_and_enc_v1_0_hw_test.tcl
 134
 135 set repo_paths [get_property ip_repo_paths [current_fileset]]
 136 if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
 137         set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
 138         update_ip_catalog
 139 }
 140
 141 set design_name ""
 142 set all_bd {}
 143 set all_bd_files [get_files *.bd -quiet]
 144 foreach file $all_bd_files {
 145 set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
 146 set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
 147 lappend all_bd $bd_name
 148 }
 149
 150 for { set i 1 } { 1 } { incr i } {
 151         set design_name "spi_leds_and_enc_v1_0_hw_${i}"
 152         if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
 153                 break
 154         }
 155 }
 156
 157 set intf_address_include_file ""
 158 create_ipi_design intf_address_include_file ${design_name}
 159 save_bd_design
 160 validate_bd_design
 161
 162 set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
 163 import_files -force -norecurse $wrapper_file
 164
 165 puts "-------------------------------------------------------------------------------------------------"
 166 puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
 167 puts "   please perform following steps to test design in targeted board."
 168 puts "1. Generate bitstream"
 169 puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
 170 puts "3. Download generated bitstream"
 171 puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
 172 puts "   to every interface present in the peripheral : xilinx.com:user:myip:1.0"
 173 puts "   : source -notrace ${hw_test_file}"
 174 puts "-------------------------------------------------------------------------------------------------"
 175