1 /* Xilinx CAN device driver
3 * Copyright (C) 2012 - 2014 Xilinx, Inc.
4 * Copyright (C) 2009 PetaLogix. All rights reserved.
7 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/clk.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/netdevice.h>
28 #include <linux/platform_device.h>
29 #include <linux/skbuff.h>
30 #include <linux/string.h>
31 #include <linux/types.h>
32 #include <linux/can/dev.h>
33 #include <linux/can/error.h>
34 #include <linux/can/led.h>
35 #include <linux/ktime.h>
36 #include <linux/net_tstamp.h>
38 #define DRIVER_NAME "xilinx_can"
40 /* CAN registers set */
42 XCAN_SRR_OFFSET = 0x00, /* Software reset */
43 XCAN_MSR_OFFSET = 0x04, /* Mode select */
44 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */
45 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */
46 XCAN_ECR_OFFSET = 0x10, /* Error counter */
47 XCAN_ESR_OFFSET = 0x14, /* Error status */
48 XCAN_SR_OFFSET = 0x18, /* Status */
49 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */
50 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */
51 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */
52 XCAN_TXFIFO_ID_OFFSET = 0x30,/* TX FIFO ID */
53 XCAN_TXFIFO_DLC_OFFSET = 0x34, /* TX FIFO DLC */
54 XCAN_TXFIFO_DW1_OFFSET = 0x38, /* TX FIFO Data Word 1 */
55 XCAN_TXFIFO_DW2_OFFSET = 0x3C, /* TX FIFO Data Word 2 */
56 XCAN_RXFIFO_ID_OFFSET = 0x50, /* RX FIFO ID */
57 XCAN_RXFIFO_DLC_OFFSET = 0x54, /* RX FIFO DLC */
58 XCAN_RXFIFO_DW1_OFFSET = 0x58, /* RX FIFO Data Word 1 */
59 XCAN_RXFIFO_DW2_OFFSET = 0x5C, /* RX FIFO Data Word 2 */
62 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
63 #define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */
64 #define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */
65 #define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */
66 #define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */
67 #define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */
68 #define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */
69 #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
70 #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */
71 #define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */
72 #define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */
73 #define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */
74 #define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */
75 #define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */
76 #define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */
77 #define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */
78 #define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */
79 #define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */
80 #define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */
81 #define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */
82 #define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */
83 #define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */
84 #define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */
85 #define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */
86 #define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */
87 #define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */
88 #define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */
89 #define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */
90 #define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */
91 #define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */
92 #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */
93 #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */
94 #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */
95 #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
96 #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
97 #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
98 #define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
99 #define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */
100 #define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */
102 #define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\
103 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \
104 XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \
105 XCAN_IXR_ARBLST_MASK | XCAN_IXR_RXOK_MASK)
107 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
108 #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
109 #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */
110 #define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
111 #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
112 #define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */
113 #define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */
115 /* CAN frame length constants */
116 #define XCAN_FRAME_MAX_DATA_LEN 8
117 #define XCAN_TIMEOUT (1 * HZ)
119 struct xcan_timepoint {
125 * struct xcan_priv - This definition define CAN driver instance
126 * @can: CAN private data structure.
127 * @tx_head: Tx CAN packets ready to send on the queue
128 * @tx_tail: Tx CAN packets successfully sended on the queue
129 * @tx_max: Maximum number packets the driver can send
130 * @napi: NAPI structure
131 * @read_reg: For reading data from CAN registers
132 * @write_reg: For writing data to CAN registers
133 * @dev: Network device data structure
134 * @reg_base: Ioremapped address to registers
135 * @irq_flags: For request_irq()
136 * @bus_clk: Pointer to struct clk
137 * @can_clk: Pointer to struct clk
138 * @ref_timepoint: Reference timepoint for synchronizing ktime with HW ticks
142 unsigned int tx_head;
143 unsigned int tx_tail;
145 struct napi_struct napi;
146 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg);
147 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
149 struct net_device *dev;
150 void __iomem *reg_base;
151 unsigned long irq_flags;
154 struct xcan_timepoint ref_timepoint;
157 /* CAN Bittiming constants as per Xilinx CAN specs */
158 static const struct can_bittiming_const xcan_bittiming_const = {
171 * xcan_write_reg_le - Write a value to the device register little endian
172 * @priv: Driver private data structure
173 * @reg: Register offset
174 * @val: Value to write at the Register offset
176 * Write data to the paricular CAN register
178 static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg,
181 iowrite32(val, priv->reg_base + reg);
185 * xcan_read_reg_le - Read a value from the device register little endian
186 * @priv: Driver private data structure
187 * @reg: Register offset
189 * Read data from the particular CAN register
190 * Return: value read from the CAN register
192 static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg)
194 return ioread32(priv->reg_base + reg);
198 * xcan_write_reg_be - Write a value to the device register big endian
199 * @priv: Driver private data structure
200 * @reg: Register offset
201 * @val: Value to write at the Register offset
203 * Write data to the paricular CAN register
205 static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg,
208 iowrite32be(val, priv->reg_base + reg);
212 * xcan_read_reg_be - Read a value from the device register big endian
213 * @priv: Driver private data structure
214 * @reg: Register offset
216 * Read data from the particular CAN register
217 * Return: value read from the CAN register
219 static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg)
221 return ioread32be(priv->reg_base + reg);
225 * set_reset_mode - Resets the CAN device mode
226 * @ndev: Pointer to net_device structure
228 * This is the driver reset mode routine.The driver
229 * enters into configuration mode.
231 * Return: 0 on success and failure value on error
233 static int set_reset_mode(struct net_device *ndev)
235 struct xcan_priv *priv = netdev_priv(ndev);
236 unsigned long timeout;
238 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
240 timeout = jiffies + XCAN_TIMEOUT;
241 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) {
242 if (time_after(jiffies, timeout)) {
243 netdev_warn(ndev, "timed out for config mode\n");
246 usleep_range(500, 10000);
253 * xcan_set_bittiming - CAN set bit timing routine
254 * @ndev: Pointer to net_device structure
256 * This is the driver set bittiming routine.
257 * Return: 0 on success and failure value on error
259 static int xcan_set_bittiming(struct net_device *ndev)
261 struct xcan_priv *priv = netdev_priv(ndev);
262 struct can_bittiming *bt = &priv->can.bittiming;
266 /* Check whether Xilinx CAN is in configuration mode.
267 * It cannot set bit timing if Xilinx CAN is not in configuration mode.
269 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) &
271 if (!is_config_mode) {
273 "BUG! Cannot set bittiming - CAN is not in config mode\n");
277 /* Setting Baud Rate prescalar value in BRPR Register */
278 btr0 = (bt->brp - 1);
280 /* Setting Time Segment 1 in BTR Register */
281 btr1 = (bt->prop_seg + bt->phase_seg1 - 1);
283 /* Setting Time Segment 2 in BTR Register */
284 btr1 |= (bt->phase_seg2 - 1) << XCAN_BTR_TS2_SHIFT;
286 /* Setting Synchronous jump width in BTR Register */
287 btr1 |= (bt->sjw - 1) << XCAN_BTR_SJW_SHIFT;
289 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
290 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
292 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
293 priv->read_reg(priv, XCAN_BRPR_OFFSET),
294 priv->read_reg(priv, XCAN_BTR_OFFSET));
300 * xcan_chip_start - This the drivers start routine
301 * @ndev: Pointer to net_device structure
303 * This is the drivers start routine.
304 * Based on the State of the CAN device it puts
305 * the CAN device into a proper mode.
307 * Return: 0 on success and failure value on error
309 static int xcan_chip_start(struct net_device *ndev)
311 struct xcan_priv *priv = netdev_priv(ndev);
312 u32 reg_msr, reg_sr_mask;
314 unsigned long timeout;
316 /* Check if it is in reset mode */
317 err = set_reset_mode(ndev);
321 err = xcan_set_bittiming(ndev);
325 /* Enable interrupts */
326 priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL);
328 /* Check whether it is loopback mode or normal mode */
329 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
330 reg_msr = XCAN_MSR_LBACK_MASK;
331 reg_sr_mask = XCAN_SR_LBACK_MASK;
334 reg_sr_mask = XCAN_SR_NORMAL_MASK;
337 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);
338 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
340 timeout = jiffies + XCAN_TIMEOUT;
341 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) {
342 if (time_after(jiffies, timeout)) {
344 "timed out for correct mode\n");
348 netdev_dbg(ndev, "status:#x%08x\n",
349 priv->read_reg(priv, XCAN_SR_OFFSET));
351 priv->can.state = CAN_STATE_ERROR_ACTIVE;
356 * xcan_do_set_mode - This sets the mode of the driver
357 * @ndev: Pointer to net_device structure
358 * @mode: Tells the mode of the driver
360 * This check the drivers state and calls the
361 * the corresponding modes to set.
363 * Return: 0 on success and failure value on error
365 static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode)
371 ret = xcan_chip_start(ndev);
373 netdev_err(ndev, "xcan_chip_start failed!\n");
376 netif_wake_queue(ndev);
387 * xcan_start_xmit - Starts the transmission
388 * @skb: sk_buff pointer that contains data to be Txed
389 * @ndev: Pointer to net_device structure
391 * This function is invoked from upper layers to initiate transmission. This
392 * function uses the next available free txbuff and populates their fields to
393 * start the transmission.
395 * Return: 0 on success and failure value on error
397 static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
399 struct xcan_priv *priv = netdev_priv(ndev);
400 struct net_device_stats *stats = &ndev->stats;
401 struct can_frame *cf = (struct can_frame *)skb->data;
402 u32 id, dlc, data[2] = {0, 0};
404 if (can_dropped_invalid_skb(ndev, skb))
407 /* Check if the TX buffer is full */
408 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) &
409 XCAN_SR_TXFLL_MASK)) {
410 netif_stop_queue(ndev);
411 netdev_err(ndev, "BUG!, TX FIFO full when queue awake!\n");
412 return NETDEV_TX_BUSY;
415 /* Watch carefully on the bit sequence */
416 if (cf->can_id & CAN_EFF_FLAG) {
417 /* Extended CAN ID format */
418 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) &
420 id |= (((cf->can_id & CAN_EFF_MASK) >>
421 (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) <<
422 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK;
424 /* The substibute remote TX request bit should be "1"
425 * for extended frames as in the Xilinx CAN datasheet
427 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK;
429 if (cf->can_id & CAN_RTR_FLAG)
430 /* Extended frames remote TX request */
431 id |= XCAN_IDR_RTR_MASK;
433 /* Standard CAN ID format */
434 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) &
437 if (cf->can_id & CAN_RTR_FLAG)
438 /* Standard frames remote TX request */
439 id |= XCAN_IDR_SRR_MASK;
442 dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT;
445 data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
447 data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
449 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
452 /* Write the Frame to Xilinx CAN TX FIFO */
453 priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id);
454 /* If the CAN frame is RTR frame this write triggers tranmission */
455 priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc);
456 if (!(cf->can_id & CAN_RTR_FLAG)) {
457 priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]);
458 /* If the CAN frame is Standard/Extended frame this
459 * write triggers tranmission
461 priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]);
462 stats->tx_bytes += cf->can_dlc;
465 /* Check if the TX buffer is full */
466 if ((priv->tx_head - priv->tx_tail) == priv->tx_max)
467 netif_stop_queue(ndev);
474 - keep (ktime_t, hwts) pair as a reference
476 now_time = get_ktime()
477 assume now_time >= frame_time >= ref_time
478 to_ns = (ts) -> ts*1e9 / bitrate
479 rollover_ktime = to_ns(65536)
480 tsdelta = (frame_ts - ref_ts) & 0xFFFF
481 if now_ktime - ref_ktime < rollover_time
482 frame_ktime = ref_time + to_ns(tsdelta)
484 nrollovers = floor((now_ktime - ref_ktime)/rollover_ktime)
485 frame_ktime = ref_ktime + nrollovers * rollover_ktime + to_ns(tsdelta)
486 if frame_ktime > now_ktime
487 frame_ktime -= rollover_ktime
488 set reference point (ref_ktime, ref_ts) = (frame_ktime, frame_ts) ??? cummulative loss of precision ? meybe not
491 static ktime_t xcan_timestamp2ktime(struct xcan_priv *priv, u16 ts, struct net_device *netdev, u32 *tmdiffns)
493 u32 freq = priv->can.clock.freq;
494 struct xcan_timepoint *ref = &priv->ref_timepoint;
498 now_ktime = ktime_get();
500 if (ktime_equal(ref->ktime, ns_to_ktime(0))) {
501 ref->ktime = now_ktime;
503 frame_ktime = now_ktime;
506 u16 tsdelta = (ts - ref->ts) & 0xFFFF;
507 #define TS2NS(ts) div_u64((ts) * (u64)1000000000, freq)
508 // nrollovers = nowdelta / rollover_ns
509 // nrollovers = nowdelta / (65536 * 1000000000 / freq)
510 // nrollovers = nowdelta * freq / (65536 * 1000000000)
511 s64 rollover_ns = TS2NS(65536);
512 ktime_t nowdelta = ktime_sub(now_ktime, ref->ktime);
513 u32 nrollovers = ktime_divns(nowdelta, rollover_ns);
514 //u32 nrollovers = ktime_divns(ns_to_ktime(ktime_to_ns(nowdelta) * freq), 65536 * 1000000000ULL);
516 frame_ktime = ktime_add_ns(ref->ktime, nrollovers * rollover_ns + TS2NS(tsdelta));
517 //frame_ktime = ktime_add_ns(ref->ktime, div_u64(((u64)nrollovers * 65536 + tsdelta) * 1000000000, freq));
518 if (ktime_after(frame_ktime, now_ktime)) {
519 frame_ktime = ktime_sub_ns(frame_ktime, rollover_ns);
521 /*netdev_warn(netdev, "TS: ftime = %llu, delay = %lld us%s; hwtime = %hu, nrollovers = %u, "
522 "tsdelta = %hu, freq = %u, ref->ktime = %llu, ref->ts = %hu, now_ktime = %llu",
523 ktime_to_ns(frame_ktime),
524 ktime_to_us(ktime_sub(now_ktime, frame_ktime)),
525 corr ? ", corr" : "",
527 nrollovers, tsdelta, freq, ref->ktime, ref->ts, now_ktime);*/
529 *tmdiffns = ktime_to_ns(ktime_sub(now_ktime, frame_ktime)) & 0xFFFFFFFF;
535 static u16 xcan_get_timestamp(u32 dlc)
542 * xcan_rx - Is called from CAN isr to complete the received
544 * @ndev: Pointer to net_device structure
546 * This function is invoked from the CAN isr(poll) to process the Rx frames. It
547 * does minimal processing and invokes "netif_receive_skb" to complete further
549 * Return: 1 on success and 0 on failure.
551 static int xcan_rx(struct net_device *ndev)
553 struct xcan_priv *priv = netdev_priv(ndev);
554 struct net_device_stats *stats = &ndev->stats;
555 struct can_frame *cf;
557 struct skb_shared_hwtstamps *hwts;
558 u32 id_xcan, dlc_reg, dlc, rawts, data[2] = {0, 0};
561 skb = alloc_can_skb(ndev, &cf);
562 if (unlikely(!skb)) {
567 /* Read a frame from Xilinx zynq CANPS */
568 id_xcan = priv->read_reg(priv, XCAN_RXFIFO_ID_OFFSET);
569 dlc_reg = priv->read_reg(priv, XCAN_RXFIFO_DLC_OFFSET);
570 dlc = dlc_reg >> XCAN_DLCR_DLC_SHIFT;
572 /* Change Xilinx CAN data length format to socketCAN data format */
573 cf->can_dlc = get_can_dlc(dlc);
575 /* Capture HW timestamp. TODO: only if requested? */
576 hwts = skb_hwtstamps(skb);
577 memset(hwts, 0, sizeof(*hwts));
578 rawts = le32_to_cpu(xcan_get_timestamp(dlc_reg));
579 hwts->hwtstamp = xcan_timestamp2ktime(priv, rawts, ndev, &tmdiffns);
581 /* Change Xilinx CAN ID format to socketCAN ID format */
582 if (id_xcan & XCAN_IDR_IDE_MASK) {
583 /* The received frame is an Extended format frame */
584 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
585 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
587 cf->can_id |= CAN_EFF_FLAG;
588 if (id_xcan & XCAN_IDR_RTR_MASK)
589 cf->can_id |= CAN_RTR_FLAG;
591 /* The received frame is a standard format frame */
592 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
594 if (id_xcan & XCAN_IDR_SRR_MASK)
595 cf->can_id |= CAN_RTR_FLAG;
598 /* DW1/DW2 must always be read to remove message from RXFIFO */
599 data[0] = priv->read_reg(priv, XCAN_RXFIFO_DW1_OFFSET);
600 data[1] = priv->read_reg(priv, XCAN_RXFIFO_DW2_OFFSET);
601 //data[1] = tmdiffns; // DBG
603 if (!(cf->can_id & CAN_RTR_FLAG)) {
604 /* Change Xilinx CAN data format to socketCAN data format */
606 *(__be32 *)(cf->data) = cpu_to_be32(data[0]);
608 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]);
611 stats->rx_bytes += cf->can_dlc;
613 netif_receive_skb(skb);
619 * xcan_err_interrupt - error frame Isr
620 * @ndev: net_device pointer
621 * @isr: interrupt status register value
623 * This is the CAN error interrupt and it will
624 * check the the type of error and forward the error
625 * frame to upper layers.
627 static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
629 struct xcan_priv *priv = netdev_priv(ndev);
630 struct net_device_stats *stats = &ndev->stats;
631 struct can_frame *cf;
633 u32 err_status, status, txerr = 0, rxerr = 0;
635 skb = alloc_can_err_skb(ndev, &cf);
637 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);
638 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
639 txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
640 rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
641 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
642 status = priv->read_reg(priv, XCAN_SR_OFFSET);
644 if (isr & XCAN_IXR_BSOFF_MASK) {
645 priv->can.state = CAN_STATE_BUS_OFF;
646 priv->can.can_stats.bus_off++;
647 /* Leave device in Config Mode in bus-off state */
648 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
651 cf->can_id |= CAN_ERR_BUSOFF;
652 } else if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) {
653 priv->can.state = CAN_STATE_ERROR_PASSIVE;
654 priv->can.can_stats.error_passive++;
656 cf->can_id |= CAN_ERR_CRTL;
657 cf->data[1] = (rxerr > 127) ?
658 CAN_ERR_CRTL_RX_PASSIVE :
659 CAN_ERR_CRTL_TX_PASSIVE;
663 } else if (status & XCAN_SR_ERRWRN_MASK) {
664 priv->can.state = CAN_STATE_ERROR_WARNING;
665 priv->can.can_stats.error_warning++;
667 cf->can_id |= CAN_ERR_CRTL;
668 cf->data[1] |= (txerr > rxerr) ?
669 CAN_ERR_CRTL_TX_WARNING :
670 CAN_ERR_CRTL_RX_WARNING;
676 /* Check for Arbitration lost interrupt */
677 if (isr & XCAN_IXR_ARBLST_MASK) {
678 priv->can.can_stats.arbitration_lost++;
680 cf->can_id |= CAN_ERR_LOSTARB;
681 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC;
685 /* Check for RX FIFO Overflow interrupt */
686 if (isr & XCAN_IXR_RXOFLW_MASK) {
687 stats->rx_over_errors++;
689 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
691 cf->can_id |= CAN_ERR_CRTL;
692 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
696 /* Check for error interrupt */
697 if (isr & XCAN_IXR_ERROR_MASK) {
699 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
701 /* Check for Ack error interrupt */
702 if (err_status & XCAN_ESR_ACKER_MASK) {
705 cf->can_id |= CAN_ERR_ACK;
706 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
710 /* Check for Bit error interrupt */
711 if (err_status & XCAN_ESR_BERR_MASK) {
714 cf->can_id |= CAN_ERR_PROT;
715 cf->data[2] = CAN_ERR_PROT_BIT;
719 /* Check for Stuff error interrupt */
720 if (err_status & XCAN_ESR_STER_MASK) {
723 cf->can_id |= CAN_ERR_PROT;
724 cf->data[2] = CAN_ERR_PROT_STUFF;
728 /* Check for Form error interrupt */
729 if (err_status & XCAN_ESR_FMER_MASK) {
732 cf->can_id |= CAN_ERR_PROT;
733 cf->data[2] = CAN_ERR_PROT_FORM;
737 /* Check for CRC error interrupt */
738 if (err_status & XCAN_ESR_CRCER_MASK) {
741 cf->can_id |= CAN_ERR_PROT;
742 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
745 priv->can.can_stats.bus_error++;
750 stats->rx_bytes += cf->can_dlc;
754 netdev_dbg(ndev, "%s: error status register:0x%x\n",
755 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET));
759 * xcan_state_interrupt - It will check the state of the CAN device
760 * @ndev: net_device pointer
761 * @isr: interrupt status register value
763 * This will checks the state of the CAN device
764 * and puts the device into appropriate state.
766 static void xcan_state_interrupt(struct net_device *ndev, u32 isr)
768 struct xcan_priv *priv = netdev_priv(ndev);
770 /* Check for Sleep interrupt if set put CAN device in sleep state */
771 if (isr & XCAN_IXR_SLP_MASK)
772 priv->can.state = CAN_STATE_SLEEPING;
774 /* Check for Wake up interrupt if set put CAN device in Active state */
775 if (isr & XCAN_IXR_WKUP_MASK)
776 priv->can.state = CAN_STATE_ERROR_ACTIVE;
780 * xcan_rx_poll - Poll routine for rx packets (NAPI)
781 * @napi: napi structure pointer
782 * @quota: Max number of rx packets to be processed.
784 * This is the poll routine for rx part.
785 * It will process the packets maximux quota value.
787 * Return: number of packets received
789 static int xcan_rx_poll(struct napi_struct *napi, int quota)
791 struct net_device *ndev = napi->dev;
792 struct xcan_priv *priv = netdev_priv(ndev);
796 //netdev_warn(ndev, "DBG: xcan_rx_poll");
797 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
798 while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) {
799 //if (isr & XCAN_IXR_RXOK_MASK) {
800 priv->write_reg(priv, XCAN_ICR_OFFSET,
802 work_done += xcan_rx(ndev);
804 priv->write_reg(priv, XCAN_ICR_OFFSET,
805 XCAN_IXR_RXNEMP_MASK);
808 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK);
809 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
813 can_led_event(ndev, CAN_LED_EVENT_RX);
815 if (work_done < quota) {
817 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
818 ier |= (XCAN_IXR_RXOK_MASK | XCAN_IXR_RXNEMP_MASK);
819 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
825 * xcan_tx_interrupt - Tx Done Isr
826 * @ndev: net_device pointer
827 * @isr: Interrupt status register value
829 static void xcan_tx_interrupt(struct net_device *ndev, u32 isr)
831 struct xcan_priv *priv = netdev_priv(ndev);
832 struct net_device_stats *stats = &ndev->stats;
834 while ((priv->tx_head - priv->tx_tail > 0) &&
835 (isr & XCAN_IXR_TXOK_MASK)) {
836 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
837 can_get_echo_skb(ndev, priv->tx_tail %
841 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
843 can_led_event(ndev, CAN_LED_EVENT_TX);
844 netif_wake_queue(ndev);
848 * xcan_interrupt - CAN Isr
850 * @dev_id: device id poniter
852 * This is the xilinx CAN Isr. It checks for the type of interrupt
853 * and invokes the corresponding ISR.
856 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
858 static irqreturn_t xcan_interrupt(int irq, void *dev_id)
860 struct net_device *ndev = (struct net_device *)dev_id;
861 struct xcan_priv *priv = netdev_priv(ndev);
864 /* Get the interrupt status from Xilinx CAN */
865 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
866 //netdev_warn(ndev, "DBG: xcan_interrupt: ISR = 0x%08x, IER = 0x%08x", isr, priv->read_reg(priv, XCAN_IER_OFFSET));
870 /* Check for the type of interrupt and Processing it */
871 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) {
872 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |
873 XCAN_IXR_WKUP_MASK));
874 xcan_state_interrupt(ndev, isr);
877 /* Check for Tx interrupt and Processing it */
878 if (isr & XCAN_IXR_TXOK_MASK)
879 xcan_tx_interrupt(ndev, isr);
881 /* Check for the type of error interrupt and Processing it */
882 if (isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
883 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK)) {
884 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK |
885 XCAN_IXR_RXOFLW_MASK | XCAN_IXR_BSOFF_MASK |
886 XCAN_IXR_ARBLST_MASK));
887 xcan_err_interrupt(ndev, isr);
890 /* Check for the type of receive interrupt and Processing it */
891 if (isr & (XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK)) {
892 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
893 ier &= ~(XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK);
894 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
895 napi_schedule(&priv->napi);
901 * xcan_chip_stop - Driver stop routine
902 * @ndev: Pointer to net_device structure
904 * This is the drivers stop routine. It will disable the
905 * interrupts and put the device into configuration mode.
907 static void xcan_chip_stop(struct net_device *ndev)
909 struct xcan_priv *priv = netdev_priv(ndev);
912 /* Disable interrupts and leave the can in configuration mode */
913 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
914 ier &= ~XCAN_INTR_ALL;
915 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
916 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
917 priv->can.state = CAN_STATE_STOPPED;
921 * xcan_open - Driver open routine
922 * @ndev: Pointer to net_device structure
924 * This is the driver open routine.
925 * Return: 0 on success and failure value on error
927 static int xcan_open(struct net_device *ndev)
929 struct xcan_priv *priv = netdev_priv(ndev);
932 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
935 netdev_err(ndev, "irq allocation for CAN failed\n");
939 ret = clk_prepare_enable(priv->can_clk);
941 netdev_err(ndev, "unable to enable device clock\n");
945 ret = clk_prepare_enable(priv->bus_clk);
947 netdev_err(ndev, "unable to enable bus clock\n");
951 /* Set chip into reset mode */
952 ret = set_reset_mode(ndev);
954 netdev_err(ndev, "mode resetting failed!\n");
959 ret = open_candev(ndev);
963 ret = xcan_chip_start(ndev);
965 netdev_err(ndev, "xcan_chip_start failed!\n");
969 can_led_event(ndev, CAN_LED_EVENT_OPEN);
970 napi_enable(&priv->napi);
971 netif_start_queue(ndev);
978 clk_disable_unprepare(priv->bus_clk);
980 clk_disable_unprepare(priv->can_clk);
982 free_irq(ndev->irq, ndev);
988 * xcan_close - Driver close routine
989 * @ndev: Pointer to net_device structure
993 static int xcan_close(struct net_device *ndev)
995 struct xcan_priv *priv = netdev_priv(ndev);
997 netif_stop_queue(ndev);
998 napi_disable(&priv->napi);
999 xcan_chip_stop(ndev);
1000 clk_disable_unprepare(priv->bus_clk);
1001 clk_disable_unprepare(priv->can_clk);
1002 free_irq(ndev->irq, ndev);
1005 can_led_event(ndev, CAN_LED_EVENT_STOP);
1011 * xcan_get_berr_counter - error counter routine
1012 * @ndev: Pointer to net_device structure
1013 * @bec: Pointer to can_berr_counter structure
1015 * This is the driver error counter routine.
1016 * Return: 0 on success and failure value on error
1018 static int xcan_get_berr_counter(const struct net_device *ndev,
1019 struct can_berr_counter *bec)
1021 struct xcan_priv *priv = netdev_priv(ndev);
1024 ret = clk_prepare_enable(priv->can_clk);
1028 ret = clk_prepare_enable(priv->bus_clk);
1032 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
1033 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
1034 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
1036 clk_disable_unprepare(priv->bus_clk);
1037 clk_disable_unprepare(priv->can_clk);
1042 clk_disable_unprepare(priv->can_clk);
1047 static int xcan_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1049 //struct xcan_priv *priv = netdev_priv(dev);
1050 struct hwtstamp_config cfg;
1052 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1055 /* reserved for future extensions */
1059 if (cfg.tx_type != HWTSTAMP_TX_OFF)
1062 switch (cfg.rx_filter) {
1063 case HWTSTAMP_FILTER_NONE:
1064 //priv->rx_enable = 0;
1066 case HWTSTAMP_FILTER_ALL:
1067 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1068 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1069 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1070 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1071 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1072 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1073 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1074 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1075 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1076 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1077 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1078 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1079 //priv->rx_enable = 1;
1080 cfg.rx_filter = HWTSTAMP_FILTER_ALL;
1086 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1089 static int xcan_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1091 //struct xcan_priv *priv = netdev_priv(dev);
1092 struct hwtstamp_config cfg;
1095 cfg.tx_type = HWTSTAMP_TX_OFF;
1096 cfg.rx_filter = //(xcan->rx_enable ?
1097 HWTSTAMP_FILTER_ALL;// : HWTSTAMP_FILTER_NONE);
1099 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1102 static int xcan_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1107 return xcan_hwtstamp_set(dev, ifr);
1109 return xcan_hwtstamp_get(dev, ifr);
1115 static const struct net_device_ops xcan_netdev_ops = {
1116 .ndo_open = xcan_open,
1117 .ndo_stop = xcan_close,
1118 .ndo_start_xmit = xcan_start_xmit,
1119 .ndo_change_mtu = can_change_mtu,
1120 .ndo_do_ioctl = xcan_ioctl,
1124 * xcan_suspend - Suspend method for the driver
1125 * @dev: Address of the platform_device structure
1127 * Put the driver into low power mode.
1130 static int __maybe_unused xcan_suspend(struct device *dev)
1132 struct platform_device *pdev = dev_get_drvdata(dev);
1133 struct net_device *ndev = platform_get_drvdata(pdev);
1134 struct xcan_priv *priv = netdev_priv(ndev);
1136 if (netif_running(ndev)) {
1137 netif_stop_queue(ndev);
1138 netif_device_detach(ndev);
1141 priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK);
1142 priv->can.state = CAN_STATE_SLEEPING;
1144 clk_disable(priv->bus_clk);
1145 clk_disable(priv->can_clk);
1151 * xcan_resume - Resume from suspend
1152 * @dev: Address of the platformdevice structure
1154 * Resume operation after suspend.
1155 * Return: 0 on success and failure value on error
1157 static int __maybe_unused xcan_resume(struct device *dev)
1159 struct platform_device *pdev = dev_get_drvdata(dev);
1160 struct net_device *ndev = platform_get_drvdata(pdev);
1161 struct xcan_priv *priv = netdev_priv(ndev);
1164 ret = clk_enable(priv->bus_clk);
1166 dev_err(dev, "Cannot enable clock.\n");
1169 ret = clk_enable(priv->can_clk);
1171 dev_err(dev, "Cannot enable clock.\n");
1172 clk_disable_unprepare(priv->bus_clk);
1176 priv->write_reg(priv, XCAN_MSR_OFFSET, 0);
1177 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
1178 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1180 if (netif_running(ndev)) {
1181 netif_device_attach(ndev);
1182 netif_start_queue(ndev);
1188 static SIMPLE_DEV_PM_OPS(xcan_dev_pm_ops, xcan_suspend, xcan_resume);
1191 * xcan_probe - Platform registration call
1192 * @pdev: Handle to the platform device structure
1194 * This function does all the memory allocation and registration for the CAN
1197 * Return: 0 on success and failure value on error
1199 static int xcan_probe(struct platform_device *pdev)
1201 struct resource *res; /* IO mem resources */
1202 struct net_device *ndev;
1203 struct xcan_priv *priv;
1205 int ret, rx_max, tx_max;
1207 /* Get the virtual base address for the device */
1208 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1209 addr = devm_ioremap_resource(&pdev->dev, res);
1211 ret = PTR_ERR(addr);
1215 ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", &tx_max);
1219 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", &rx_max);
1223 /* Create a CAN device instance */
1224 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max);
1228 priv = netdev_priv(ndev);
1230 priv->can.bittiming_const = &xcan_bittiming_const;
1231 priv->can.do_set_mode = xcan_do_set_mode;
1232 priv->can.do_get_berr_counter = xcan_get_berr_counter;
1233 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1234 CAN_CTRLMODE_BERR_REPORTING;
1235 priv->reg_base = addr;
1236 priv->tx_max = tx_max;
1238 /* Get IRQ for the device */
1239 ndev->irq = platform_get_irq(pdev, 0);
1240 ndev->flags |= IFF_ECHO; /* We support local echo */
1242 platform_set_drvdata(pdev, ndev);
1243 SET_NETDEV_DEV(ndev, &pdev->dev);
1244 ndev->netdev_ops = &xcan_netdev_ops;
1246 /* Getting the CAN can_clk info */
1247 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1248 if (IS_ERR(priv->can_clk)) {
1249 dev_err(&pdev->dev, "Device clock not found.\n");
1250 ret = PTR_ERR(priv->can_clk);
1253 /* Check for type of CAN device */
1254 if (of_device_is_compatible(pdev->dev.of_node,
1255 "xlnx,zynq-can-1.0")) {
1256 priv->bus_clk = devm_clk_get(&pdev->dev, "pclk");
1257 if (IS_ERR(priv->bus_clk)) {
1258 dev_err(&pdev->dev, "bus clock not found\n");
1259 ret = PTR_ERR(priv->bus_clk);
1263 priv->bus_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
1264 if (IS_ERR(priv->bus_clk)) {
1265 dev_err(&pdev->dev, "bus clock not found\n");
1266 ret = PTR_ERR(priv->bus_clk);
1271 ret = clk_prepare_enable(priv->can_clk);
1273 dev_err(&pdev->dev, "unable to enable device clock\n");
1277 ret = clk_prepare_enable(priv->bus_clk);
1279 dev_err(&pdev->dev, "unable to enable bus clock\n");
1280 goto err_unprepare_disable_dev;
1283 priv->write_reg = xcan_write_reg_le;
1284 priv->read_reg = xcan_read_reg_le;
1286 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {
1287 priv->write_reg = xcan_write_reg_be;
1288 priv->read_reg = xcan_read_reg_be;
1291 priv->can.clock.freq = clk_get_rate(priv->can_clk);
1293 netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max);
1295 ret = register_candev(ndev);
1297 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret);
1298 goto err_unprepare_disable_busclk;
1301 devm_can_led_init(ndev);
1302 clk_disable_unprepare(priv->bus_clk);
1303 clk_disable_unprepare(priv->can_clk);
1304 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n",
1305 priv->reg_base, ndev->irq, priv->can.clock.freq,
1310 err_unprepare_disable_busclk:
1311 clk_disable_unprepare(priv->bus_clk);
1312 err_unprepare_disable_dev:
1313 clk_disable_unprepare(priv->can_clk);
1321 * xcan_remove - Unregister the device after releasing the resources
1322 * @pdev: Handle to the platform device structure
1324 * This function frees all the resources allocated to the device.
1327 static int xcan_remove(struct platform_device *pdev)
1329 struct net_device *ndev = platform_get_drvdata(pdev);
1330 struct xcan_priv *priv = netdev_priv(ndev);
1332 if (set_reset_mode(ndev) < 0)
1333 netdev_err(ndev, "mode resetting failed!\n");
1335 unregister_candev(ndev);
1336 netif_napi_del(&priv->napi);
1342 /* Match table for OF platform binding */
1343 static const struct of_device_id xcan_of_match[] = {
1344 { .compatible = "xlnx,zynq-can-1.0", },
1345 { .compatible = "xlnx,axi-can-1.00.a", },
1346 { /* end of list */ },
1348 MODULE_DEVICE_TABLE(of, xcan_of_match);
1350 static struct platform_driver xcan_driver = {
1351 .probe = xcan_probe,
1352 .remove = xcan_remove,
1354 .name = DRIVER_NAME,
1355 .pm = &xcan_dev_pm_ops,
1356 .of_match_table = xcan_of_match,
1360 module_platform_driver(xcan_driver);
1362 MODULE_LICENSE("GPL");
1363 MODULE_AUTHOR("Xilinx Inc");
1364 MODULE_DESCRIPTION("Xilinx CAN interface");