1 /* Xilinx CAN device driver
3 * Copyright (C) 2012 - 2014 Xilinx, Inc.
4 * Copyright (C) 2009 PetaLogix. All rights reserved.
7 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/clk.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/netdevice.h>
28 #include <linux/platform_device.h>
29 #include <linux/skbuff.h>
30 #include <linux/string.h>
31 #include <linux/types.h>
32 #include <linux/can/dev.h>
33 #include <linux/can/error.h>
34 #include <linux/can/led.h>
35 #include <linux/ktime.h>
36 #include <linux/net_tstamp.h>
38 #define DRIVER_NAME "xilinx_can"
40 /* CAN registers set */
42 XCAN_SRR_OFFSET = 0x00, /* Software reset */
43 XCAN_MSR_OFFSET = 0x04, /* Mode select */
44 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */
45 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */
46 XCAN_ECR_OFFSET = 0x10, /* Error counter */
47 XCAN_ESR_OFFSET = 0x14, /* Error status */
48 XCAN_SR_OFFSET = 0x18, /* Status */
49 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */
50 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */
51 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */
52 XCAN_TXFIFO_ID_OFFSET = 0x30,/* TX FIFO ID */
53 XCAN_TXFIFO_DLC_OFFSET = 0x34, /* TX FIFO DLC */
54 XCAN_TXFIFO_DW1_OFFSET = 0x38, /* TX FIFO Data Word 1 */
55 XCAN_TXFIFO_DW2_OFFSET = 0x3C, /* TX FIFO Data Word 2 */
56 XCAN_RXFIFO_ID_OFFSET = 0x50, /* RX FIFO ID */
57 XCAN_RXFIFO_DLC_OFFSET = 0x54, /* RX FIFO DLC */
58 XCAN_RXFIFO_DW1_OFFSET = 0x58, /* RX FIFO Data Word 1 */
59 XCAN_RXFIFO_DW2_OFFSET = 0x5C, /* RX FIFO Data Word 2 */
62 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
63 #define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */
64 #define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */
65 #define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */
66 #define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */
67 #define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */
68 #define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */
69 #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
70 #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */
71 #define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */
72 #define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */
73 #define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */
74 #define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */
75 #define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */
76 #define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */
77 #define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */
78 #define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */
79 #define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */
80 #define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */
81 #define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */
82 #define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */
83 #define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */
84 #define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */
85 #define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */
86 #define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */
87 #define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */
88 #define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */
89 #define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */
90 #define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */
91 #define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */
92 #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */
93 #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */
94 #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */
95 #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
96 #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
97 #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
98 #define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
99 #define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */
100 #define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */
102 #define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\
103 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \
104 XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \
105 XCAN_IXR_ARBLST_MASK | XCAN_IXR_RXOK_MASK)
107 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
108 #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
109 #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */
110 #define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
111 #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
112 #define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */
113 #define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */
115 /* CAN frame length constants */
116 #define XCAN_FRAME_MAX_DATA_LEN 8
117 #define XCAN_TIMEOUT (1 * HZ)
119 struct xcan_timepoint {
125 * struct xcan_priv - This definition define CAN driver instance
126 * @can: CAN private data structure.
127 * @tx_head: Tx CAN packets ready to send on the queue
128 * @tx_tail: Tx CAN packets successfully sended on the queue
129 * @tx_max: Maximum number packets the driver can send
130 * @napi: NAPI structure
131 * @read_reg: For reading data from CAN registers
132 * @write_reg: For writing data to CAN registers
133 * @dev: Network device data structure
134 * @reg_base: Ioremapped address to registers
135 * @irq_flags: For request_irq()
136 * @bus_clk: Pointer to struct clk
137 * @can_clk: Pointer to struct clk
138 * @ref_timepoint: Reference timepoint for synchronizing ktime with HW ticks
142 unsigned int tx_head;
143 unsigned int tx_tail;
145 struct napi_struct napi;
146 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg);
147 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
149 struct net_device *dev;
150 void __iomem *reg_base;
151 unsigned long irq_flags;
154 struct xcan_timepoint ref_timepoint;
157 /* CAN Bittiming constants as per Xilinx CAN specs */
158 static const struct can_bittiming_const xcan_bittiming_const = {
171 * xcan_write_reg_le - Write a value to the device register little endian
172 * @priv: Driver private data structure
173 * @reg: Register offset
174 * @val: Value to write at the Register offset
176 * Write data to the paricular CAN register
178 static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg,
181 iowrite32(val, priv->reg_base + reg);
185 * xcan_read_reg_le - Read a value from the device register little endian
186 * @priv: Driver private data structure
187 * @reg: Register offset
189 * Read data from the particular CAN register
190 * Return: value read from the CAN register
192 static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg)
194 return ioread32(priv->reg_base + reg);
198 * xcan_write_reg_be - Write a value to the device register big endian
199 * @priv: Driver private data structure
200 * @reg: Register offset
201 * @val: Value to write at the Register offset
203 * Write data to the paricular CAN register
205 static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg,
208 iowrite32be(val, priv->reg_base + reg);
212 * xcan_read_reg_be - Read a value from the device register big endian
213 * @priv: Driver private data structure
214 * @reg: Register offset
216 * Read data from the particular CAN register
217 * Return: value read from the CAN register
219 static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg)
221 return ioread32be(priv->reg_base + reg);
225 * set_reset_mode - Resets the CAN device mode
226 * @ndev: Pointer to net_device structure
228 * This is the driver reset mode routine.The driver
229 * enters into configuration mode.
231 * Return: 0 on success and failure value on error
233 static int set_reset_mode(struct net_device *ndev)
235 struct xcan_priv *priv = netdev_priv(ndev);
236 unsigned long timeout;
238 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
240 timeout = jiffies + XCAN_TIMEOUT;
241 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) {
242 if (time_after(jiffies, timeout)) {
243 netdev_warn(ndev, "timed out for config mode\n");
246 usleep_range(500, 10000);
253 * xcan_set_bittiming - CAN set bit timing routine
254 * @ndev: Pointer to net_device structure
256 * This is the driver set bittiming routine.
257 * Return: 0 on success and failure value on error
259 static int xcan_set_bittiming(struct net_device *ndev)
261 struct xcan_priv *priv = netdev_priv(ndev);
262 struct can_bittiming *bt = &priv->can.bittiming;
266 /* Check whether Xilinx CAN is in configuration mode.
267 * It cannot set bit timing if Xilinx CAN is not in configuration mode.
269 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) &
271 if (!is_config_mode) {
273 "BUG! Cannot set bittiming - CAN is not in config mode\n");
277 /* Setting Baud Rate prescalar value in BRPR Register */
278 btr0 = (bt->brp - 1);
280 /* Setting Time Segment 1 in BTR Register */
281 btr1 = (bt->prop_seg + bt->phase_seg1 - 1);
283 /* Setting Time Segment 2 in BTR Register */
284 btr1 |= (bt->phase_seg2 - 1) << XCAN_BTR_TS2_SHIFT;
286 /* Setting Synchronous jump width in BTR Register */
287 btr1 |= (bt->sjw - 1) << XCAN_BTR_SJW_SHIFT;
289 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
290 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
292 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
293 priv->read_reg(priv, XCAN_BRPR_OFFSET),
294 priv->read_reg(priv, XCAN_BTR_OFFSET));
300 * xcan_chip_start - This the drivers start routine
301 * @ndev: Pointer to net_device structure
303 * This is the drivers start routine.
304 * Based on the State of the CAN device it puts
305 * the CAN device into a proper mode.
307 * Return: 0 on success and failure value on error
309 static int xcan_chip_start(struct net_device *ndev)
311 struct xcan_priv *priv = netdev_priv(ndev);
312 u32 reg_msr, reg_sr_mask;
314 unsigned long timeout;
316 /* Check if it is in reset mode */
317 err = set_reset_mode(ndev);
321 err = xcan_set_bittiming(ndev);
325 /* Enable interrupts */
326 priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL);
328 /* Check whether it is loopback mode or normal mode */
329 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
330 reg_msr = XCAN_MSR_LBACK_MASK;
331 reg_sr_mask = XCAN_SR_LBACK_MASK;
334 reg_sr_mask = XCAN_SR_NORMAL_MASK;
337 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);
338 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
340 timeout = jiffies + XCAN_TIMEOUT;
341 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) {
342 if (time_after(jiffies, timeout)) {
344 "timed out for correct mode\n");
348 netdev_dbg(ndev, "status:#x%08x\n",
349 priv->read_reg(priv, XCAN_SR_OFFSET));
351 priv->can.state = CAN_STATE_ERROR_ACTIVE;
356 * xcan_do_set_mode - This sets the mode of the driver
357 * @ndev: Pointer to net_device structure
358 * @mode: Tells the mode of the driver
360 * This check the drivers state and calls the
361 * the corresponding modes to set.
363 * Return: 0 on success and failure value on error
365 static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode)
371 ret = xcan_chip_start(ndev);
373 netdev_err(ndev, "xcan_chip_start failed!\n");
376 netif_wake_queue(ndev);
387 * xcan_start_xmit - Starts the transmission
388 * @skb: sk_buff pointer that contains data to be Txed
389 * @ndev: Pointer to net_device structure
391 * This function is invoked from upper layers to initiate transmission. This
392 * function uses the next available free txbuff and populates their fields to
393 * start the transmission.
395 * Return: 0 on success and failure value on error
397 static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
399 struct xcan_priv *priv = netdev_priv(ndev);
400 struct net_device_stats *stats = &ndev->stats;
401 struct can_frame *cf = (struct can_frame *)skb->data;
402 u32 id, dlc, data[2] = {0, 0};
404 if (can_dropped_invalid_skb(ndev, skb))
407 /* Check if the TX buffer is full */
408 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) &
409 XCAN_SR_TXFLL_MASK)) {
410 netif_stop_queue(ndev);
411 netdev_err(ndev, "BUG!, TX FIFO full when queue awake!\n");
412 return NETDEV_TX_BUSY;
415 /* Watch carefully on the bit sequence */
416 if (cf->can_id & CAN_EFF_FLAG) {
417 /* Extended CAN ID format */
418 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) &
420 id |= (((cf->can_id & CAN_EFF_MASK) >>
421 (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) <<
422 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK;
424 /* The substibute remote TX request bit should be "1"
425 * for extended frames as in the Xilinx CAN datasheet
427 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK;
429 if (cf->can_id & CAN_RTR_FLAG)
430 /* Extended frames remote TX request */
431 id |= XCAN_IDR_RTR_MASK;
433 /* Standard CAN ID format */
434 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) &
437 if (cf->can_id & CAN_RTR_FLAG)
438 /* Standard frames remote TX request */
439 id |= XCAN_IDR_SRR_MASK;
442 dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT;
445 data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
447 data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
449 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
452 /* Write the Frame to Xilinx CAN TX FIFO */
453 priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id);
454 /* If the CAN frame is RTR frame this write triggers tranmission */
455 priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc);
456 if (!(cf->can_id & CAN_RTR_FLAG)) {
457 priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]);
458 /* If the CAN frame is Standard/Extended frame this
459 * write triggers tranmission
461 priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]);
462 stats->tx_bytes += cf->can_dlc;
465 /* Check if the TX buffer is full */
466 if ((priv->tx_head - priv->tx_tail) == priv->tx_max)
467 netif_stop_queue(ndev);
474 - keep (ktime_t, hwts) pair as a reference
476 now_time = get_ktime()
477 assume now_time >= frame_time >= ref_time
478 to_ns = (ts) -> ts*1e9 / bitrate
479 rollover_ktime = to_ns(65536)
480 tsdelta = (frame_ts - ref_ts) & 0xFFFF
481 if now_ktime - ref_ktime < rollover_time
482 frame_ktime = ref_time + to_ns(tsdelta)
484 nrollovers = floor((now_ktime - ref_ktime)/rollover_ktime)
485 frame_ktime = ref_ktime + nrollovers * rollover_ktime + to_ns(tsdelta)
486 if frame_ktime > now_ktime
487 frame_ktime -= rollover_ktime
488 set reference point (ref_ktime, ref_ts) = (frame_ktime, frame_ts) ??? cummulative loss of precision ? meybe not
491 static ktime_t xcan_timestamp2ktime(struct xcan_priv *priv, u16 ts)
493 u32 bitrate = priv->can.bittiming.bitrate; // TODO: I once saw a function for this ...
494 struct xcan_timepoint *ref = &priv->ref_timepoint;
495 ktime_t now_ktime = ktime_get();
498 if (ktime_equal(ref->ktime, ns_to_ktime(0))) {
499 ref->ktime = now_ktime;
501 frame_ktime = now_ktime;
503 u16 tsdelta = (ts - ref->ts) & 0xFFFF;
504 #define TS2NS(ts) ({ u64 tmp = (ts) * (u64)1000000000; do_div(tmp, bitrate); tmp; })
505 s64 rollover_ns = TS2NS(ts);
506 ktime_t nowdelta = ktime_sub(now_ktime, ref->ktime);
507 u32 nrollovers = ktime_divns(nowdelta, rollover_ns);
509 frame_ktime = ktime_add_ns(ref->ktime, nrollovers * rollover_ns + TS2NS(tsdelta));
510 if (ktime_after(frame_ktime, now_ktime)) {
511 frame_ktime = ktime_sub_ns(frame_ktime, rollover_ns);
518 static u16 xcan_get_timestamp(u32 dlc)
520 // TODO: endianity conversion?
526 * xcan_rx - Is called from CAN isr to complete the received
528 * @ndev: Pointer to net_device structure
530 * This function is invoked from the CAN isr(poll) to process the Rx frames. It
531 * does minimal processing and invokes "netif_receive_skb" to complete further
533 * Return: 1 on success and 0 on failure.
535 static int xcan_rx(struct net_device *ndev)
537 struct xcan_priv *priv = netdev_priv(ndev);
538 struct net_device_stats *stats = &ndev->stats;
539 struct can_frame *cf;
541 struct skb_shared_hwtstamps *hwts;
542 u32 id_xcan, dlc, data[2] = {0, 0};
545 skb = alloc_can_skb(ndev, &cf);
546 if (unlikely(!skb)) {
551 /* Read a frame from Xilinx zynq CANPS */
552 id_xcan = priv->read_reg(priv, XCAN_RXFIFO_ID_OFFSET);
553 dlc = priv->read_reg(priv, XCAN_RXFIFO_DLC_OFFSET) >>
556 /* Change Xilinx CAN data length format to socketCAN data format */
557 cf->can_dlc = get_can_dlc(dlc);
559 /* Capture HW timestamp. TODO: only if requested? */
560 hwts = skb_hwtstamps(skb);
561 memset(hwts, 0, sizeof(*hwts));
562 ts = xcan_timestamp2ktime(priv, le32_to_cpu(xcan_get_timestamp(dlc)));
564 netdev_dbg(ndev, "Frame timestamp: raw %hu, transformed %lld ns", xcan_get_timestamp(dlc), ktime_to_ns(ts));
566 /* Change Xilinx CAN ID format to socketCAN ID format */
567 if (id_xcan & XCAN_IDR_IDE_MASK) {
568 /* The received frame is an Extended format frame */
569 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
570 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
572 cf->can_id |= CAN_EFF_FLAG;
573 if (id_xcan & XCAN_IDR_RTR_MASK)
574 cf->can_id |= CAN_RTR_FLAG;
576 /* The received frame is a standard format frame */
577 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
579 if (id_xcan & XCAN_IDR_SRR_MASK)
580 cf->can_id |= CAN_RTR_FLAG;
583 /* DW1/DW2 must always be read to remove message from RXFIFO */
584 data[0] = priv->read_reg(priv, XCAN_RXFIFO_DW1_OFFSET);
585 data[1] = priv->read_reg(priv, XCAN_RXFIFO_DW2_OFFSET);
587 if (!(cf->can_id & CAN_RTR_FLAG)) {
588 /* Change Xilinx CAN data format to socketCAN data format */
590 *(__be32 *)(cf->data) = cpu_to_be32(data[0]);
592 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]);
595 stats->rx_bytes += cf->can_dlc;
597 netif_receive_skb(skb);
603 * xcan_err_interrupt - error frame Isr
604 * @ndev: net_device pointer
605 * @isr: interrupt status register value
607 * This is the CAN error interrupt and it will
608 * check the the type of error and forward the error
609 * frame to upper layers.
611 static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
613 struct xcan_priv *priv = netdev_priv(ndev);
614 struct net_device_stats *stats = &ndev->stats;
615 struct can_frame *cf;
617 u32 err_status, status, txerr = 0, rxerr = 0;
619 skb = alloc_can_err_skb(ndev, &cf);
621 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);
622 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
623 txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
624 rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
625 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
626 status = priv->read_reg(priv, XCAN_SR_OFFSET);
628 if (isr & XCAN_IXR_BSOFF_MASK) {
629 priv->can.state = CAN_STATE_BUS_OFF;
630 priv->can.can_stats.bus_off++;
631 /* Leave device in Config Mode in bus-off state */
632 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
635 cf->can_id |= CAN_ERR_BUSOFF;
636 } else if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) {
637 priv->can.state = CAN_STATE_ERROR_PASSIVE;
638 priv->can.can_stats.error_passive++;
640 cf->can_id |= CAN_ERR_CRTL;
641 cf->data[1] = (rxerr > 127) ?
642 CAN_ERR_CRTL_RX_PASSIVE :
643 CAN_ERR_CRTL_TX_PASSIVE;
647 } else if (status & XCAN_SR_ERRWRN_MASK) {
648 priv->can.state = CAN_STATE_ERROR_WARNING;
649 priv->can.can_stats.error_warning++;
651 cf->can_id |= CAN_ERR_CRTL;
652 cf->data[1] |= (txerr > rxerr) ?
653 CAN_ERR_CRTL_TX_WARNING :
654 CAN_ERR_CRTL_RX_WARNING;
660 /* Check for Arbitration lost interrupt */
661 if (isr & XCAN_IXR_ARBLST_MASK) {
662 priv->can.can_stats.arbitration_lost++;
664 cf->can_id |= CAN_ERR_LOSTARB;
665 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC;
669 /* Check for RX FIFO Overflow interrupt */
670 if (isr & XCAN_IXR_RXOFLW_MASK) {
671 stats->rx_over_errors++;
673 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
675 cf->can_id |= CAN_ERR_CRTL;
676 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
680 /* Check for error interrupt */
681 if (isr & XCAN_IXR_ERROR_MASK) {
683 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
685 /* Check for Ack error interrupt */
686 if (err_status & XCAN_ESR_ACKER_MASK) {
689 cf->can_id |= CAN_ERR_ACK;
690 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
694 /* Check for Bit error interrupt */
695 if (err_status & XCAN_ESR_BERR_MASK) {
698 cf->can_id |= CAN_ERR_PROT;
699 cf->data[2] = CAN_ERR_PROT_BIT;
703 /* Check for Stuff error interrupt */
704 if (err_status & XCAN_ESR_STER_MASK) {
707 cf->can_id |= CAN_ERR_PROT;
708 cf->data[2] = CAN_ERR_PROT_STUFF;
712 /* Check for Form error interrupt */
713 if (err_status & XCAN_ESR_FMER_MASK) {
716 cf->can_id |= CAN_ERR_PROT;
717 cf->data[2] = CAN_ERR_PROT_FORM;
721 /* Check for CRC error interrupt */
722 if (err_status & XCAN_ESR_CRCER_MASK) {
725 cf->can_id |= CAN_ERR_PROT;
726 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
729 priv->can.can_stats.bus_error++;
734 stats->rx_bytes += cf->can_dlc;
738 netdev_dbg(ndev, "%s: error status register:0x%x\n",
739 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET));
743 * xcan_state_interrupt - It will check the state of the CAN device
744 * @ndev: net_device pointer
745 * @isr: interrupt status register value
747 * This will checks the state of the CAN device
748 * and puts the device into appropriate state.
750 static void xcan_state_interrupt(struct net_device *ndev, u32 isr)
752 struct xcan_priv *priv = netdev_priv(ndev);
754 /* Check for Sleep interrupt if set put CAN device in sleep state */
755 if (isr & XCAN_IXR_SLP_MASK)
756 priv->can.state = CAN_STATE_SLEEPING;
758 /* Check for Wake up interrupt if set put CAN device in Active state */
759 if (isr & XCAN_IXR_WKUP_MASK)
760 priv->can.state = CAN_STATE_ERROR_ACTIVE;
764 * xcan_rx_poll - Poll routine for rx packets (NAPI)
765 * @napi: napi structure pointer
766 * @quota: Max number of rx packets to be processed.
768 * This is the poll routine for rx part.
769 * It will process the packets maximux quota value.
771 * Return: number of packets received
773 static int xcan_rx_poll(struct napi_struct *napi, int quota)
775 struct net_device *ndev = napi->dev;
776 struct xcan_priv *priv = netdev_priv(ndev);
780 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
781 while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) {
782 if (isr & XCAN_IXR_RXOK_MASK) {
783 priv->write_reg(priv, XCAN_ICR_OFFSET,
785 work_done += xcan_rx(ndev);
787 priv->write_reg(priv, XCAN_ICR_OFFSET,
788 XCAN_IXR_RXNEMP_MASK);
791 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK);
792 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
796 can_led_event(ndev, CAN_LED_EVENT_RX);
798 if (work_done < quota) {
800 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
801 ier |= (XCAN_IXR_RXOK_MASK | XCAN_IXR_RXNEMP_MASK);
802 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
808 * xcan_tx_interrupt - Tx Done Isr
809 * @ndev: net_device pointer
810 * @isr: Interrupt status register value
812 static void xcan_tx_interrupt(struct net_device *ndev, u32 isr)
814 struct xcan_priv *priv = netdev_priv(ndev);
815 struct net_device_stats *stats = &ndev->stats;
817 while ((priv->tx_head - priv->tx_tail > 0) &&
818 (isr & XCAN_IXR_TXOK_MASK)) {
819 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
820 can_get_echo_skb(ndev, priv->tx_tail %
824 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
826 can_led_event(ndev, CAN_LED_EVENT_TX);
827 netif_wake_queue(ndev);
831 * xcan_interrupt - CAN Isr
833 * @dev_id: device id poniter
835 * This is the xilinx CAN Isr. It checks for the type of interrupt
836 * and invokes the corresponding ISR.
839 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
841 static irqreturn_t xcan_interrupt(int irq, void *dev_id)
843 struct net_device *ndev = (struct net_device *)dev_id;
844 struct xcan_priv *priv = netdev_priv(ndev);
847 /* Get the interrupt status from Xilinx CAN */
848 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
852 /* Check for the type of interrupt and Processing it */
853 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) {
854 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |
855 XCAN_IXR_WKUP_MASK));
856 xcan_state_interrupt(ndev, isr);
859 /* Check for Tx interrupt and Processing it */
860 if (isr & XCAN_IXR_TXOK_MASK)
861 xcan_tx_interrupt(ndev, isr);
863 /* Check for the type of error interrupt and Processing it */
864 if (isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
865 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK)) {
866 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK |
867 XCAN_IXR_RXOFLW_MASK | XCAN_IXR_BSOFF_MASK |
868 XCAN_IXR_ARBLST_MASK));
869 xcan_err_interrupt(ndev, isr);
872 /* Check for the type of receive interrupt and Processing it */
873 if (isr & (XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK)) {
874 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
875 ier &= ~(XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK);
876 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
877 napi_schedule(&priv->napi);
883 * xcan_chip_stop - Driver stop routine
884 * @ndev: Pointer to net_device structure
886 * This is the drivers stop routine. It will disable the
887 * interrupts and put the device into configuration mode.
889 static void xcan_chip_stop(struct net_device *ndev)
891 struct xcan_priv *priv = netdev_priv(ndev);
894 /* Disable interrupts and leave the can in configuration mode */
895 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
896 ier &= ~XCAN_INTR_ALL;
897 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
898 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
899 priv->can.state = CAN_STATE_STOPPED;
903 * xcan_open - Driver open routine
904 * @ndev: Pointer to net_device structure
906 * This is the driver open routine.
907 * Return: 0 on success and failure value on error
909 static int xcan_open(struct net_device *ndev)
911 struct xcan_priv *priv = netdev_priv(ndev);
914 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
917 netdev_err(ndev, "irq allocation for CAN failed\n");
921 ret = clk_prepare_enable(priv->can_clk);
923 netdev_err(ndev, "unable to enable device clock\n");
927 ret = clk_prepare_enable(priv->bus_clk);
929 netdev_err(ndev, "unable to enable bus clock\n");
933 /* Set chip into reset mode */
934 ret = set_reset_mode(ndev);
936 netdev_err(ndev, "mode resetting failed!\n");
941 ret = open_candev(ndev);
945 ret = xcan_chip_start(ndev);
947 netdev_err(ndev, "xcan_chip_start failed!\n");
951 can_led_event(ndev, CAN_LED_EVENT_OPEN);
952 napi_enable(&priv->napi);
953 netif_start_queue(ndev);
960 clk_disable_unprepare(priv->bus_clk);
962 clk_disable_unprepare(priv->can_clk);
964 free_irq(ndev->irq, ndev);
970 * xcan_close - Driver close routine
971 * @ndev: Pointer to net_device structure
975 static int xcan_close(struct net_device *ndev)
977 struct xcan_priv *priv = netdev_priv(ndev);
979 netif_stop_queue(ndev);
980 napi_disable(&priv->napi);
981 xcan_chip_stop(ndev);
982 clk_disable_unprepare(priv->bus_clk);
983 clk_disable_unprepare(priv->can_clk);
984 free_irq(ndev->irq, ndev);
987 can_led_event(ndev, CAN_LED_EVENT_STOP);
993 * xcan_get_berr_counter - error counter routine
994 * @ndev: Pointer to net_device structure
995 * @bec: Pointer to can_berr_counter structure
997 * This is the driver error counter routine.
998 * Return: 0 on success and failure value on error
1000 static int xcan_get_berr_counter(const struct net_device *ndev,
1001 struct can_berr_counter *bec)
1003 struct xcan_priv *priv = netdev_priv(ndev);
1006 ret = clk_prepare_enable(priv->can_clk);
1010 ret = clk_prepare_enable(priv->bus_clk);
1014 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
1015 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
1016 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
1018 clk_disable_unprepare(priv->bus_clk);
1019 clk_disable_unprepare(priv->can_clk);
1024 clk_disable_unprepare(priv->can_clk);
1029 static int xcan_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1031 //struct xcan_priv *priv = netdev_priv(dev);
1032 struct hwtstamp_config cfg;
1034 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1037 /* reserved for future extensions */
1041 if (cfg.tx_type != HWTSTAMP_TX_OFF)
1044 switch (cfg.rx_filter) {
1045 case HWTSTAMP_FILTER_NONE:
1046 //priv->rx_enable = 0;
1048 case HWTSTAMP_FILTER_ALL:
1049 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1050 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1051 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1052 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1053 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1054 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1055 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1056 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1057 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1058 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1059 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1060 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1061 //priv->rx_enable = 1;
1062 cfg.rx_filter = HWTSTAMP_FILTER_ALL;
1068 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1071 static int xcan_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1073 //struct xcan_priv *priv = netdev_priv(dev);
1074 struct hwtstamp_config cfg;
1077 cfg.tx_type = HWTSTAMP_TX_OFF;
1078 cfg.rx_filter = //(xcan->rx_enable ?
1079 HWTSTAMP_FILTER_ALL;// : HWTSTAMP_FILTER_NONE);
1081 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1084 static int xcan_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1089 return xcan_hwtstamp_set(dev, ifr);
1091 return xcan_hwtstamp_get(dev, ifr);
1097 static const struct net_device_ops xcan_netdev_ops = {
1098 .ndo_open = xcan_open,
1099 .ndo_stop = xcan_close,
1100 .ndo_start_xmit = xcan_start_xmit,
1101 .ndo_change_mtu = can_change_mtu,
1102 .ndo_do_ioctl = xcan_ioctl,
1106 * xcan_suspend - Suspend method for the driver
1107 * @dev: Address of the platform_device structure
1109 * Put the driver into low power mode.
1112 static int __maybe_unused xcan_suspend(struct device *dev)
1114 struct platform_device *pdev = dev_get_drvdata(dev);
1115 struct net_device *ndev = platform_get_drvdata(pdev);
1116 struct xcan_priv *priv = netdev_priv(ndev);
1118 if (netif_running(ndev)) {
1119 netif_stop_queue(ndev);
1120 netif_device_detach(ndev);
1123 priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK);
1124 priv->can.state = CAN_STATE_SLEEPING;
1126 clk_disable(priv->bus_clk);
1127 clk_disable(priv->can_clk);
1133 * xcan_resume - Resume from suspend
1134 * @dev: Address of the platformdevice structure
1136 * Resume operation after suspend.
1137 * Return: 0 on success and failure value on error
1139 static int __maybe_unused xcan_resume(struct device *dev)
1141 struct platform_device *pdev = dev_get_drvdata(dev);
1142 struct net_device *ndev = platform_get_drvdata(pdev);
1143 struct xcan_priv *priv = netdev_priv(ndev);
1146 ret = clk_enable(priv->bus_clk);
1148 dev_err(dev, "Cannot enable clock.\n");
1151 ret = clk_enable(priv->can_clk);
1153 dev_err(dev, "Cannot enable clock.\n");
1154 clk_disable_unprepare(priv->bus_clk);
1158 priv->write_reg(priv, XCAN_MSR_OFFSET, 0);
1159 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
1160 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1162 if (netif_running(ndev)) {
1163 netif_device_attach(ndev);
1164 netif_start_queue(ndev);
1170 static SIMPLE_DEV_PM_OPS(xcan_dev_pm_ops, xcan_suspend, xcan_resume);
1173 * xcan_probe - Platform registration call
1174 * @pdev: Handle to the platform device structure
1176 * This function does all the memory allocation and registration for the CAN
1179 * Return: 0 on success and failure value on error
1181 static int xcan_probe(struct platform_device *pdev)
1183 struct resource *res; /* IO mem resources */
1184 struct net_device *ndev;
1185 struct xcan_priv *priv;
1187 int ret, rx_max, tx_max;
1189 /* Get the virtual base address for the device */
1190 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1191 addr = devm_ioremap_resource(&pdev->dev, res);
1193 ret = PTR_ERR(addr);
1197 ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", &tx_max);
1201 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", &rx_max);
1205 /* Create a CAN device instance */
1206 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max);
1210 priv = netdev_priv(ndev);
1212 priv->can.bittiming_const = &xcan_bittiming_const;
1213 priv->can.do_set_mode = xcan_do_set_mode;
1214 priv->can.do_get_berr_counter = xcan_get_berr_counter;
1215 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1216 CAN_CTRLMODE_BERR_REPORTING;
1217 priv->reg_base = addr;
1218 priv->tx_max = tx_max;
1220 /* Get IRQ for the device */
1221 ndev->irq = platform_get_irq(pdev, 0);
1222 ndev->flags |= IFF_ECHO; /* We support local echo */
1224 platform_set_drvdata(pdev, ndev);
1225 SET_NETDEV_DEV(ndev, &pdev->dev);
1226 ndev->netdev_ops = &xcan_netdev_ops;
1228 /* Getting the CAN can_clk info */
1229 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1230 if (IS_ERR(priv->can_clk)) {
1231 dev_err(&pdev->dev, "Device clock not found.\n");
1232 ret = PTR_ERR(priv->can_clk);
1235 /* Check for type of CAN device */
1236 if (of_device_is_compatible(pdev->dev.of_node,
1237 "xlnx,zynq-can-1.0")) {
1238 priv->bus_clk = devm_clk_get(&pdev->dev, "pclk");
1239 if (IS_ERR(priv->bus_clk)) {
1240 dev_err(&pdev->dev, "bus clock not found\n");
1241 ret = PTR_ERR(priv->bus_clk);
1245 priv->bus_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
1246 if (IS_ERR(priv->bus_clk)) {
1247 dev_err(&pdev->dev, "bus clock not found\n");
1248 ret = PTR_ERR(priv->bus_clk);
1253 ret = clk_prepare_enable(priv->can_clk);
1255 dev_err(&pdev->dev, "unable to enable device clock\n");
1259 ret = clk_prepare_enable(priv->bus_clk);
1261 dev_err(&pdev->dev, "unable to enable bus clock\n");
1262 goto err_unprepare_disable_dev;
1265 priv->write_reg = xcan_write_reg_le;
1266 priv->read_reg = xcan_read_reg_le;
1268 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {
1269 priv->write_reg = xcan_write_reg_be;
1270 priv->read_reg = xcan_read_reg_be;
1273 priv->can.clock.freq = clk_get_rate(priv->can_clk);
1275 netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max);
1277 ret = register_candev(ndev);
1279 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret);
1280 goto err_unprepare_disable_busclk;
1283 devm_can_led_init(ndev);
1284 clk_disable_unprepare(priv->bus_clk);
1285 clk_disable_unprepare(priv->can_clk);
1286 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n",
1287 priv->reg_base, ndev->irq, priv->can.clock.freq,
1292 err_unprepare_disable_busclk:
1293 clk_disable_unprepare(priv->bus_clk);
1294 err_unprepare_disable_dev:
1295 clk_disable_unprepare(priv->can_clk);
1303 * xcan_remove - Unregister the device after releasing the resources
1304 * @pdev: Handle to the platform device structure
1306 * This function frees all the resources allocated to the device.
1309 static int xcan_remove(struct platform_device *pdev)
1311 struct net_device *ndev = platform_get_drvdata(pdev);
1312 struct xcan_priv *priv = netdev_priv(ndev);
1314 if (set_reset_mode(ndev) < 0)
1315 netdev_err(ndev, "mode resetting failed!\n");
1317 unregister_candev(ndev);
1318 netif_napi_del(&priv->napi);
1324 /* Match table for OF platform binding */
1325 static const struct of_device_id xcan_of_match[] = {
1326 { .compatible = "xlnx,zynq-can-1.0", },
1327 { .compatible = "xlnx,axi-can-1.00.a", },
1328 { /* end of list */ },
1330 MODULE_DEVICE_TABLE(of, xcan_of_match);
1332 static struct platform_driver xcan_driver = {
1333 .probe = xcan_probe,
1334 .remove = xcan_remove,
1336 .name = DRIVER_NAME,
1337 .pm = &xcan_dev_pm_ops,
1338 .of_match_table = xcan_of_match,
1342 module_platform_driver(xcan_driver);
1344 MODULE_LICENSE("GPL");
1345 MODULE_AUTHOR("Xilinx Inc");
1346 MODULE_DESCRIPTION("Xilinx CAN interface");