system/ip/sja1000_1.0/hdl/can_ifc_wb.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  can_top.v                                                   ////
   4 ////                                                              ////
   5 ////                                                              ////
   6 ////  This file is part of the CAN Protocol Controller            ////
   7 ////  http://www.opencores.org/projects/can/                      ////
   8 ////                                                              ////
   9 ////                                                              ////
  10 ////  Author(s):                                                  ////
  11 ////       Igor Mohor                                             ////
  12 ////       igorm@opencores.org                                    ////
  13 ////       Martin Jerabek                                         ////
  14 ////       jerabma7@fel.cvut.cz                                   ////
  15 ////                                                              ////
  16 ////                                                              ////
  17 ////  All additional information is available in the README.txt   ////
  18 ////  file.                                                       ////
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  20 //////////////////////////////////////////////////////////////////////
  21 ////                                                              ////
  22 //// Copyright (C) 2002, 2003, 2004 Authors                       ////
  23 ////                                                              ////
  24 //// This source file may be used and distributed without         ////
  25 //// restriction provided that this copyright statement is not    ////
  26 //// removed from the file and that any derivative work contains  ////
  27 //// the original copyright notice and the associated disclaimer. ////
  28 ////                                                              ////
  29 //// This source file is free software; you can redistribute it   ////
  30 //// and/or modify it under the terms of the GNU Lesser General   ////
  31 //// Public License as published by the Free Software Foundation; ////
  32 //// either version 2.1 of the License, or (at your option) any   ////
  33 //// later version.                                               ////
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  35 //// This source is distributed in the hope that it will be       ////
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  37 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  38 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  39 //// details.                                                     ////
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  43 //// from http://www.opencores.org/lgpl.shtml                     ////
  44 ////                                                              ////
  45 //// The CAN protocol is developed by Robert Bosch GmbH and       ////
  46 //// protected by patents. Anybody who wants to implement this    ////
  47 //// CAN IP core on silicon has to obtain a CAN protocol license  ////
  48 //// from Bosch.                                                  ////
  49 ////                                                              ////
  50 //////////////////////////////////////////////////////////////////////
  51
  52 // synopsys translate_off
  53 `include "timescale.v"
  54 // synopsys translate_on
  55 `include "can_defines.v"
  56
  57 module can_ifc_wb
  58 (
  59   clk_i,
  60   reg_rst_o,
  61   reg_cs_o,
  62   reg_we_o,
  63   reg_addr_o,
  64   reg_data_in_o,
  65   reg_data_out_i,
  66
  67   wb_clk_i,
  68   wb_rst_i,
  69   wb_dat_i,
  70   wb_dat_o,
  71   wb_cyc_i,
  72   wb_stb_i,
  73   wb_we_i,
  74   wb_adr_i,
  75   wb_ack_o,
  76 );
  77
  78 parameter Tp = 1;
  79
  80
  81   input        wb_clk_i;
  82   input        wb_rst_i;
  83   input  [7:0] wb_dat_i;
  84   output [7:0] wb_dat_o;
  85   input        wb_cyc_i;
  86   input        wb_stb_i;
  87   input        wb_we_i;
  88   input  [7:0] wb_adr_i;
  89   output       wb_ack_o;
  90
  91   input        clk_i;
  92   output       reg_rst_o;
  93   output       reg_cs_o;
  94   output       reg_we_o;
  95   output [7:0] reg_data_in_o;
  96   input  [7:0] reg_data_out_i;
  97
  98   reg          wb_ack_o;
  99   reg          cs_sync1;
 100   reg          cs_sync2;
 101   reg          cs_sync3;
 102
 103   reg          cs_ack1;
 104   reg          cs_ack2;
 105   reg          cs_ack3;
 106   reg          cs_sync_rst1;
 107   reg          cs_sync_rst2;
 108   wire         cs_can_i;
 109
 110   assign cs_can_i = 1'b1;
 111
 112   // Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain.
 113   always @ (posedge clk_i or posedge rst)
 114   begin
 115     if (rst)
 116       begin
 117         cs_sync1     <= 1'b0;
 118         cs_sync2     <= 1'b0;
 119         cs_sync3     <= 1'b0;
 120         cs_sync_rst1 <= 1'b0;
 121         cs_sync_rst2 <= 1'b0;
 122       end
 123     else
 124       begin
 125         cs_sync1     <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2) & cs_can_i;
 126         cs_sync2     <=#Tp cs_sync1            & (~cs_sync_rst2);
 127         cs_sync3     <=#Tp cs_sync2            & (~cs_sync_rst2);
 128         cs_sync_rst1 <=#Tp cs_ack3;
 129         cs_sync_rst2 <=#Tp cs_sync_rst1;
 130       end
 131   end
 132
 133
 134   assign reg_cs_o = cs_sync2 & (~cs_sync3);
 135
 136
 137   always @ (posedge wb_clk_i)
 138   begin
 139     cs_ack1 <=#Tp cs_sync3;
 140     cs_ack2 <=#Tp cs_ack1;
 141     cs_ack3 <=#Tp cs_ack2;
 142   end
 143
 144
 145
 146   // Generating acknowledge signal
 147   always @ (posedge wb_clk_i)
 148   begin
 149     wb_ack_o <=#Tp (cs_ack2 & (~cs_ack3));
 150   end
 151
 152
 153   assign reg_rst_o      = wb_rst_i;
 154   assign reg_we_o       = wb_we_i;
 155   assign reg_addr_o     = wb_adr_i;
 156   assign reg_data_in_o  = wb_dat_i;
 157   assign wb_dat_o       = reg_data_out_i;
 158
 159 endmodule