system/ip/sja1000_1.0/hdl/sja1000.v

   1 `include "timescale.v"
   2
   3         module sja1000 #
   4         (
   5                 // Users to add parameters here
   6
   7                 // User parameters ends
   8                 // Do not modify the parameters beyond this line
   9
  10
  11                 // Parameters of Axi Slave Bus Interface S00_AXI
  12                 parameter integer C_S00_AXI_DATA_WIDTH  = 32,
  13                 parameter integer C_S00_AXI_ADDR_WIDTH  = 8
  14
  15                 // Parameters of Axi Slave Bus Interface S_AXI_INTR
  16                 /*
  17                 parameter integer C_S_AXI_INTR_DATA_WIDTH       = 32,
  18                 parameter integer C_S_AXI_INTR_ADDR_WIDTH       = 5,
  19                 parameter integer C_NUM_OF_INTR = 1,
  20                 parameter  C_INTR_SENSITIVITY   = 32'hFFFFFFFF,
  21                 parameter  C_INTR_ACTIVE_STATE  = 32'hFFFFFFFF,
  22                 parameter integer C_IRQ_SENSITIVITY     = 1,
  23                 parameter integer C_IRQ_ACTIVE_STATE    = 1
  24                 */
  25         )
  26         (
  27                 // Users to add ports here
  28                 input  wire can_clk,
  29                 input  wire can_rx,
  30                 output wire can_tx,
  31                 output wire bus_off_on,
  32                 // User ports ends
  33                 // Do not modify the ports beyond this line
  34
  35
  36                 // Ports of Axi Slave Bus Interface S00_AXI
  37                 input wire  s00_axi_aclk,
  38                 input wire  s00_axi_aresetn,
  39                 input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
  40                 input wire [2 : 0] s00_axi_awprot,
  41                 input wire  s00_axi_awvalid,
  42                 output wire  s00_axi_awready,
  43                 input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
  44                 input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
  45                 input wire  s00_axi_wvalid,
  46                 output wire  s00_axi_wready,
  47                 output wire [1 : 0] s00_axi_bresp,
  48                 output wire  s00_axi_bvalid,
  49                 input wire  s00_axi_bready,
  50                 input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
  51                 input wire [2 : 0] s00_axi_arprot,
  52                 input wire  s00_axi_arvalid,
  53                 output wire  s00_axi_arready,
  54                 output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
  55                 output wire [1 : 0] s00_axi_rresp,
  56                 output wire  s00_axi_rvalid,
  57                 input wire  s00_axi_rready,
  58
  59                 output wire  irq
  60         );
  61         wire reg_we;
  62         wire reg_cs;
  63         wire reg_rst;
  64         wire [7:0] reg_data_in;
  65         wire [7:0] reg_data_out;
  66         wire [7:0] reg_addr_read;
  67         wire [7:0] reg_addr_write;
  68
  69         wire irq_n;
  70         assign irq = ~irq_n;
  71
  72 // Instantiation of Axi Bus Interface S00_AXI
  73         can_ifc_axi_sync_duplex # (
  74                 .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
  75                 .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
  76         ) can_ifc_axi_inst (
  77                 .S_AXI_ACLK(s00_axi_aclk),
  78                 .S_AXI_ARESETN(s00_axi_aresetn),
  79                 .S_AXI_AWADDR(s00_axi_awaddr),
  80                 .S_AXI_AWPROT(s00_axi_awprot),
  81                 .S_AXI_AWVALID(s00_axi_awvalid),
  82                 .S_AXI_AWREADY(s00_axi_awready),
  83                 .S_AXI_WDATA(s00_axi_wdata),
  84                 .S_AXI_WSTRB(s00_axi_wstrb),
  85                 .S_AXI_WVALID(s00_axi_wvalid),
  86                 .S_AXI_WREADY(s00_axi_wready),
  87                 .S_AXI_BRESP(s00_axi_bresp),
  88                 .S_AXI_BVALID(s00_axi_bvalid),
  89                 .S_AXI_BREADY(s00_axi_bready),
  90                 .S_AXI_ARADDR(s00_axi_araddr),
  91                 .S_AXI_ARPROT(s00_axi_arprot),
  92                 .S_AXI_ARVALID(s00_axi_arvalid),
  93                 .S_AXI_ARREADY(s00_axi_arready),
  94                 .S_AXI_RDATA(s00_axi_rdata),
  95                 .S_AXI_RRESP(s00_axi_rresp),
  96                 .S_AXI_RVALID(s00_axi_rvalid),
  97                 .S_AXI_RREADY(s00_axi_rready),
  98
  99                 //.clk_i(can_clk),
 100                 .reg_rst_o(reg_rst),
 101                 .reg_re_o(reg_re),
 102                 .reg_we_o(reg_we),
 103                 .reg_addr_read_o(reg_addr_read),
 104                 .reg_addr_write_o(reg_addr_write),
 105                 .reg_data_in_o(reg_data_in),
 106                 .reg_data_out_i(reg_data_out)
 107         );
 108
 109         can_top_raw can_top_raw_inst (
 110                 .reg_we_i(reg_we),
 111                 .reg_re_i(reg_re),
 112                 .reg_data_in(reg_data_in),
 113                 .reg_data_out(reg_data_out),
 114                 .reg_addr_read_i(reg_addr_read),
 115                 .reg_addr_write_i(reg_addr_write),
 116                 .reg_rst_i(reg_rst),
 117
 118                 .clk_i(can_clk),
 119                 .rx_i(can_rx),
 120                 .tx_o(can_tx),
 121                 .bus_off_on(bus_off_on),
 122                 .irq_on(irq_n),
 123                 .clkout_o()
 124         );
 125
 126         // Add user logic here
 127
 128         // User logic ends
 129
 130         endmodule