1 /* Xilinx CAN device driver
3 * Copyright (C) 2012 - 2014 Xilinx, Inc.
4 * Copyright (C) 2009 PetaLogix. All rights reserved.
7 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/clk.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/netdevice.h>
28 #include <linux/platform_device.h>
29 #include <linux/skbuff.h>
30 #include <linux/string.h>
31 #include <linux/types.h>
32 #include <linux/can/dev.h>
33 #include <linux/can/error.h>
34 #include <linux/can/led.h>
35 #include <linux/ktime.h>
36 #include <linux/net_tstamp.h>
38 #define DRIVER_NAME "xilinx_can"
40 /* CAN registers set */
42 XCAN_SRR_OFFSET = 0x00, /* Software reset */
43 XCAN_MSR_OFFSET = 0x04, /* Mode select */
44 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */
45 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */
46 XCAN_ECR_OFFSET = 0x10, /* Error counter */
47 XCAN_ESR_OFFSET = 0x14, /* Error status */
48 XCAN_SR_OFFSET = 0x18, /* Status */
49 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */
50 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */
51 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */
52 XCAN_TXFIFO_ID_OFFSET = 0x30,/* TX FIFO ID */
53 XCAN_TXFIFO_DLC_OFFSET = 0x34, /* TX FIFO DLC */
54 XCAN_TXFIFO_DW1_OFFSET = 0x38, /* TX FIFO Data Word 1 */
55 XCAN_TXFIFO_DW2_OFFSET = 0x3C, /* TX FIFO Data Word 2 */
56 XCAN_RXFIFO_ID_OFFSET = 0x50, /* RX FIFO ID */
57 XCAN_RXFIFO_DLC_OFFSET = 0x54, /* RX FIFO DLC */
58 XCAN_RXFIFO_DW1_OFFSET = 0x58, /* RX FIFO Data Word 1 */
59 XCAN_RXFIFO_DW2_OFFSET = 0x5C, /* RX FIFO Data Word 2 */
62 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
63 #define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */
64 #define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */
65 #define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */
66 #define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */
67 #define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */
68 #define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */
69 #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
70 #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */
71 #define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */
72 #define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */
73 #define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */
74 #define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */
75 #define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */
76 #define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */
77 #define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */
78 #define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */
79 #define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */
80 #define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */
81 #define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */
82 #define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */
83 #define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */
84 #define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */
85 #define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */
86 #define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */
87 #define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */
88 #define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */
89 #define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */
90 #define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */
91 #define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */
92 #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */
93 #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */
94 #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */
95 #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
96 #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
97 #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
98 #define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
99 #define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */
100 #define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */
102 #define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\
103 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \
104 XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \
105 XCAN_IXR_ARBLST_MASK | XCAN_IXR_RXOK_MASK)
107 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
108 #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
109 #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */
110 #define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
111 #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
112 #define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */
113 #define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */
115 /* CAN frame length constants */
116 #define XCAN_FRAME_MAX_DATA_LEN 8
117 #define XCAN_TIMEOUT (1 * HZ)
119 struct xcan_timepoint {
125 * struct xcan_priv - This definition define CAN driver instance
126 * @can: CAN private data structure.
127 * @tx_head: Tx CAN packets ready to send on the queue
128 * @tx_tail: Tx CAN packets successfully sended on the queue
129 * @tx_max: Maximum number packets the driver can send
130 * @napi: NAPI structure
131 * @read_reg: For reading data from CAN registers
132 * @write_reg: For writing data to CAN registers
133 * @dev: Network device data structure
134 * @reg_base: Ioremapped address to registers
135 * @irq_flags: For request_irq()
136 * @bus_clk: Pointer to struct clk
137 * @can_clk: Pointer to struct clk
138 * @ref_timepoint: Reference timepoint for synchronizing ktime with HW ticks
142 unsigned int tx_head;
143 unsigned int tx_tail;
145 struct napi_struct napi;
146 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg);
147 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
149 struct net_device *dev;
150 void __iomem *reg_base;
151 unsigned long irq_flags;
154 struct xcan_timepoint ref_timepoint;
162 /* CAN Bittiming constants as per Xilinx CAN specs */
163 static const struct can_bittiming_const xcan_bittiming_const = {
176 * xcan_write_reg_le - Write a value to the device register little endian
177 * @priv: Driver private data structure
178 * @reg: Register offset
179 * @val: Value to write at the Register offset
181 * Write data to the paricular CAN register
183 static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg,
186 iowrite32(val, priv->reg_base + reg);
190 * xcan_read_reg_le - Read a value from the device register little endian
191 * @priv: Driver private data structure
192 * @reg: Register offset
194 * Read data from the particular CAN register
195 * Return: value read from the CAN register
197 static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg)
199 return ioread32(priv->reg_base + reg);
203 * xcan_write_reg_be - Write a value to the device register big endian
204 * @priv: Driver private data structure
205 * @reg: Register offset
206 * @val: Value to write at the Register offset
208 * Write data to the paricular CAN register
210 static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg,
213 iowrite32be(val, priv->reg_base + reg);
217 * xcan_read_reg_be - Read a value from the device register big endian
218 * @priv: Driver private data structure
219 * @reg: Register offset
221 * Read data from the particular CAN register
222 * Return: value read from the CAN register
224 static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg)
226 return ioread32be(priv->reg_base + reg);
230 * set_reset_mode - Resets the CAN device mode
231 * @ndev: Pointer to net_device structure
233 * This is the driver reset mode routine.The driver
234 * enters into configuration mode.
236 * Return: 0 on success and failure value on error
238 static int set_reset_mode(struct net_device *ndev)
240 struct xcan_priv *priv = netdev_priv(ndev);
241 unsigned long timeout;
243 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
245 timeout = jiffies + XCAN_TIMEOUT;
246 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) {
247 if (time_after(jiffies, timeout)) {
248 netdev_warn(ndev, "timed out for config mode\n");
251 usleep_range(500, 10000);
258 * xcan_set_bittiming - CAN set bit timing routine
259 * @ndev: Pointer to net_device structure
261 * This is the driver set bittiming routine.
262 * Return: 0 on success and failure value on error
264 static int xcan_set_bittiming(struct net_device *ndev)
266 struct xcan_priv *priv = netdev_priv(ndev);
267 struct can_bittiming *bt = &priv->can.bittiming;
271 /* Check whether Xilinx CAN is in configuration mode.
272 * It cannot set bit timing if Xilinx CAN is not in configuration mode.
274 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) &
276 if (!is_config_mode) {
278 "BUG! Cannot set bittiming - CAN is not in config mode\n");
282 /* Setting Baud Rate prescalar value in BRPR Register */
283 btr0 = (bt->brp - 1);
285 /* Setting Time Segment 1 in BTR Register */
286 btr1 = (bt->prop_seg + bt->phase_seg1 - 1);
288 /* Setting Time Segment 2 in BTR Register */
289 btr1 |= (bt->phase_seg2 - 1) << XCAN_BTR_TS2_SHIFT;
291 /* Setting Synchronous jump width in BTR Register */
292 btr1 |= (bt->sjw - 1) << XCAN_BTR_SJW_SHIFT;
294 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
295 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
297 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
298 priv->read_reg(priv, XCAN_BRPR_OFFSET),
299 priv->read_reg(priv, XCAN_BTR_OFFSET));
305 * xcan_chip_start - This the drivers start routine
306 * @ndev: Pointer to net_device structure
308 * This is the drivers start routine.
309 * Based on the State of the CAN device it puts
310 * the CAN device into a proper mode.
312 * Return: 0 on success and failure value on error
314 static int xcan_chip_start(struct net_device *ndev)
316 struct xcan_priv *priv = netdev_priv(ndev);
317 u32 reg_msr, reg_sr_mask;
319 unsigned long timeout;
321 /* Check if it is in reset mode */
322 err = set_reset_mode(ndev);
326 err = xcan_set_bittiming(ndev);
330 /* Enable interrupts */
331 priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL);
333 /* Check whether it is loopback mode or normal mode */
334 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
335 reg_msr = XCAN_MSR_LBACK_MASK;
336 reg_sr_mask = XCAN_SR_LBACK_MASK;
339 reg_sr_mask = XCAN_SR_NORMAL_MASK;
342 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);
343 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
345 timeout = jiffies + XCAN_TIMEOUT;
346 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) {
347 if (time_after(jiffies, timeout)) {
349 "timed out for correct mode\n");
353 netdev_dbg(ndev, "status:#x%08x\n",
354 priv->read_reg(priv, XCAN_SR_OFFSET));
356 priv->can.state = CAN_STATE_ERROR_ACTIVE;
361 * xcan_do_set_mode - This sets the mode of the driver
362 * @ndev: Pointer to net_device structure
363 * @mode: Tells the mode of the driver
365 * This check the drivers state and calls the
366 * the corresponding modes to set.
368 * Return: 0 on success and failure value on error
370 static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode)
376 ret = xcan_chip_start(ndev);
378 netdev_err(ndev, "xcan_chip_start failed!\n");
381 netif_wake_queue(ndev);
392 * xcan_start_xmit - Starts the transmission
393 * @skb: sk_buff pointer that contains data to be Txed
394 * @ndev: Pointer to net_device structure
396 * This function is invoked from upper layers to initiate transmission. This
397 * function uses the next available free txbuff and populates their fields to
398 * start the transmission.
400 * Return: 0 on success and failure value on error
402 static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
404 struct xcan_priv *priv = netdev_priv(ndev);
405 struct net_device_stats *stats = &ndev->stats;
406 struct can_frame *cf = (struct can_frame *)skb->data;
407 u32 id, dlc, data[2] = {0, 0};
409 if (can_dropped_invalid_skb(ndev, skb))
412 /* Check if the TX buffer is full */
413 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) &
414 XCAN_SR_TXFLL_MASK)) {
415 netif_stop_queue(ndev);
416 netdev_err(ndev, "BUG!, TX FIFO full when queue awake!\n");
417 return NETDEV_TX_BUSY;
420 /* Watch carefully on the bit sequence */
421 if (cf->can_id & CAN_EFF_FLAG) {
422 /* Extended CAN ID format */
423 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) &
425 id |= (((cf->can_id & CAN_EFF_MASK) >>
426 (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) <<
427 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK;
429 /* The substibute remote TX request bit should be "1"
430 * for extended frames as in the Xilinx CAN datasheet
432 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK;
434 if (cf->can_id & CAN_RTR_FLAG)
435 /* Extended frames remote TX request */
436 id |= XCAN_IDR_RTR_MASK;
438 /* Standard CAN ID format */
439 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) &
442 if (cf->can_id & CAN_RTR_FLAG)
443 /* Standard frames remote TX request */
444 id |= XCAN_IDR_SRR_MASK;
447 dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT;
450 data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
452 data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
454 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
457 /* Write the Frame to Xilinx CAN TX FIFO */
458 priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id);
459 /* If the CAN frame is RTR frame this write triggers tranmission */
460 priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc);
461 if (!(cf->can_id & CAN_RTR_FLAG)) {
462 priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]);
463 /* If the CAN frame is Standard/Extended frame this
464 * write triggers tranmission
466 priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]);
467 stats->tx_bytes += cf->can_dlc;
470 /* Check if the TX buffer is full */
471 if ((priv->tx_head - priv->tx_tail) == priv->tx_max)
472 netif_stop_queue(ndev);
479 - keep (ktime_t, hwts) pair as a reference
481 now_time = get_ktime()
482 assume now_time >= frame_time >= ref_time
483 to_ns = (ts) -> ts*1e9 / bitrate
484 rollover_ktime = to_ns(65536)
485 tsdelta = (frame_ts - ref_ts) & 0xFFFF
486 if now_ktime - ref_ktime < rollover_time
487 frame_ktime = ref_time + to_ns(tsdelta)
489 nrollovers = floor((now_ktime - ref_ktime)/rollover_ktime)
490 frame_ktime = ref_ktime + nrollovers * rollover_ktime + to_ns(tsdelta)
491 // must do fuzzy compare - the synchronization is not exact and so the frame_time
492 may actually be before now_time and still not be in the next period, just because
493 the latency between actual_frame_time and now_time may be lower than when
494 it was for the first frame, about which it was assumed the two times happened in the same moment
495 So compare it against half the period to be safe.
496 if frame_ktime > now_ktime
497 frame_ktime -= rollover_ktime
498 set reference point (ref_ktime, ref_ts) = (frame_ktime, frame_ts) ??? cummulative loss of precision ? meybe not
501 static ktime_t xcan_timestamp2ktime(struct xcan_priv *priv, u16 ts, struct net_device *netdev, u32 *tmdiffns)
503 u32 freq = priv->can.clock.freq;
504 struct xcan_timepoint *ref = &priv->ref_timepoint;
508 ktime_now = ktime_get();
511 if (ktime_equal(ref->ktime, ns_to_ktime(0))) {
512 ref->ktime = ktime_now;
514 ktime_frame = ktime_now;
518 u16 tsdelta = (ts - ref->ts) & 0xFFFF;
519 #define TS2NS(ts) div_u64((ts) * (u64)1000000000, freq)
520 s64 rollover_ns = TS2NS(65536);
521 ktime_t nowdelta = ktime_sub(ktime_now, ref->ktime);
522 s64 nrollovers = ktime_divns(nowdelta, rollover_ns);
524 ktime_frame = ktime_add_ns(ref->ktime, nrollovers * rollover_ns + TS2NS(tsdelta));
526 diff_us = ktime_to_us(ktime_sub(ktime_now, ktime_frame));
527 diff_us = diff_us < 0 ? -diff_us : diff_us;
529 /* If the (magnitude of) delay is greater than quarter */
530 /* the period, the frame arrived in previous period */
531 if (diff_us*1000*4 > rollover_ns) {
532 ktime_frame = ktime_sub_ns(ktime_frame, rollover_ns);
535 netdev_warn(netdev, "TS: ftime = %llu, delay = %lld us; hwtime = %hu, nrollovers = %llu, "
537 ktime_to_ns(ktime_frame),
538 ktime_to_us(ktime_sub(ktime_now, ktime_frame)),
540 nrollovers, ktime_to_ns(ktime_now));
542 *tmdiffns = ktime_to_ns(ktime_sub(ktime_now, ktime_frame)) & 0xFFFFFFFF;
546 if (ktime_equal(ref->ktime, ns_to_ktime(0))) {
547 ref->ktime = ktime_now;
551 u64 cantime_frame; // TODO: 32bit enough?
552 u16 cantime_lsw_frame;
555 cantime_frame = div_u64(ktime_to_ns(ktime_sub(ktime_now, ref->ktime)), priv->cantime2ns_mul) + ref->ts;
556 //cantime_frame = ((ktime_to_ns(ktime_sub(ktime_now, ref->ktime)) * priv->ns2cantime_mul) >> priv->ns2cantime_shr) + ref->ts;
558 cantime_lsw_frame = cantime_frame & 0xffff;
559 cantime_adj = ts - cantime_lsw_frame;
560 cantime_frame += cantime_adj;
562 ktime_frame = ktime_add_ns(ref->ktime, ((u64)(cantime_frame - ref->ts) * priv->cantime2ns_mul) >> priv->cantime2ns_shr);
564 //*tmdiffns = (s32)(ktime_to_ns(ktime_sub(ktime_now, ktime_frame)) & 0xFFFFFFFF);
565 *tmdiffns = (s32)cantime_adj * 50;
567 //ref->ktime = ktime_frame;
570 /* adjust reference */
571 //ref->ktime = ktime_sub_ns(ref->ktime, ((s32)cantime_adj * (s32)priv->cantime2ns_mul) >> (priv->cantime2ns_shr + 7));
577 static u16 xcan_get_timestamp(u32 dlc)
584 * xcan_rx - Is called from CAN isr to complete the received
586 * @ndev: Pointer to net_device structure
588 * This function is invoked from the CAN isr(poll) to process the Rx frames. It
589 * does minimal processing and invokes "netif_receive_skb" to complete further
591 * Return: 1 on success and 0 on failure.
593 static int xcan_rx(struct net_device *ndev)
595 struct xcan_priv *priv = netdev_priv(ndev);
596 struct net_device_stats *stats = &ndev->stats;
597 struct can_frame *cf;
599 struct skb_shared_hwtstamps *hwts;
600 u32 id_xcan, dlc_reg, dlc, rawts, data[2] = {0, 0};
603 skb = alloc_can_skb(ndev, &cf);
604 if (unlikely(!skb)) {
609 /* Read a frame from Xilinx zynq CANPS */
610 id_xcan = priv->read_reg(priv, XCAN_RXFIFO_ID_OFFSET);
611 dlc_reg = priv->read_reg(priv, XCAN_RXFIFO_DLC_OFFSET);
612 dlc = dlc_reg >> XCAN_DLCR_DLC_SHIFT;
614 /* Change Xilinx CAN data length format to socketCAN data format */
615 cf->can_dlc = get_can_dlc(dlc);
617 /* Capture HW timestamp. TODO: only if requested? */
618 hwts = skb_hwtstamps(skb);
619 memset(hwts, 0, sizeof(*hwts));
620 rawts = le32_to_cpu(xcan_get_timestamp(dlc_reg));
621 hwts->hwtstamp = xcan_timestamp2ktime(priv, rawts, ndev, &tmdiffns);
623 /* Change Xilinx CAN ID format to socketCAN ID format */
624 if (id_xcan & XCAN_IDR_IDE_MASK) {
625 /* The received frame is an Extended format frame */
626 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
627 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
629 cf->can_id |= CAN_EFF_FLAG;
630 if (id_xcan & XCAN_IDR_RTR_MASK)
631 cf->can_id |= CAN_RTR_FLAG;
633 /* The received frame is a standard format frame */
634 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
636 if (id_xcan & XCAN_IDR_SRR_MASK)
637 cf->can_id |= CAN_RTR_FLAG;
640 /* DW1/DW2 must always be read to remove message from RXFIFO */
641 data[0] = priv->read_reg(priv, XCAN_RXFIFO_DW1_OFFSET);
642 data[1] = priv->read_reg(priv, XCAN_RXFIFO_DW2_OFFSET);
644 data[0] = (data[0] & 0xFFFF0000) | (u16)((s16)(rawts - priv->ref_timepoint.ts)); // DBG
645 data[1] = tmdiffns; // DBG
646 cf->can_dlc = 8; // DBG
649 if (!(cf->can_id & CAN_RTR_FLAG)) {
650 /* Change Xilinx CAN data format to socketCAN data format */
652 *(__be32 *)(cf->data) = cpu_to_be32(data[0]);
654 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]);
657 stats->rx_bytes += cf->can_dlc;
659 netif_receive_skb(skb);
665 * xcan_err_interrupt - error frame Isr
666 * @ndev: net_device pointer
667 * @isr: interrupt status register value
669 * This is the CAN error interrupt and it will
670 * check the the type of error and forward the error
671 * frame to upper layers.
673 static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
675 struct xcan_priv *priv = netdev_priv(ndev);
676 struct net_device_stats *stats = &ndev->stats;
677 struct can_frame *cf;
679 u32 err_status, status, txerr = 0, rxerr = 0;
681 skb = alloc_can_err_skb(ndev, &cf);
683 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);
684 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
685 txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
686 rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
687 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
688 status = priv->read_reg(priv, XCAN_SR_OFFSET);
690 if (isr & XCAN_IXR_BSOFF_MASK) {
691 priv->can.state = CAN_STATE_BUS_OFF;
692 priv->can.can_stats.bus_off++;
693 /* Leave device in Config Mode in bus-off state */
694 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
697 cf->can_id |= CAN_ERR_BUSOFF;
698 } else if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) {
699 priv->can.state = CAN_STATE_ERROR_PASSIVE;
700 priv->can.can_stats.error_passive++;
702 cf->can_id |= CAN_ERR_CRTL;
703 cf->data[1] = (rxerr > 127) ?
704 CAN_ERR_CRTL_RX_PASSIVE :
705 CAN_ERR_CRTL_TX_PASSIVE;
709 } else if (status & XCAN_SR_ERRWRN_MASK) {
710 priv->can.state = CAN_STATE_ERROR_WARNING;
711 priv->can.can_stats.error_warning++;
713 cf->can_id |= CAN_ERR_CRTL;
714 cf->data[1] |= (txerr > rxerr) ?
715 CAN_ERR_CRTL_TX_WARNING :
716 CAN_ERR_CRTL_RX_WARNING;
722 /* Check for Arbitration lost interrupt */
723 if (isr & XCAN_IXR_ARBLST_MASK) {
724 priv->can.can_stats.arbitration_lost++;
726 cf->can_id |= CAN_ERR_LOSTARB;
727 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC;
731 /* Check for RX FIFO Overflow interrupt */
732 if (isr & XCAN_IXR_RXOFLW_MASK) {
733 stats->rx_over_errors++;
735 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
737 cf->can_id |= CAN_ERR_CRTL;
738 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
742 /* Check for error interrupt */
743 if (isr & XCAN_IXR_ERROR_MASK) {
745 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
747 /* Check for Ack error interrupt */
748 if (err_status & XCAN_ESR_ACKER_MASK) {
751 cf->can_id |= CAN_ERR_ACK;
752 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
756 /* Check for Bit error interrupt */
757 if (err_status & XCAN_ESR_BERR_MASK) {
760 cf->can_id |= CAN_ERR_PROT;
761 cf->data[2] = CAN_ERR_PROT_BIT;
765 /* Check for Stuff error interrupt */
766 if (err_status & XCAN_ESR_STER_MASK) {
769 cf->can_id |= CAN_ERR_PROT;
770 cf->data[2] = CAN_ERR_PROT_STUFF;
774 /* Check for Form error interrupt */
775 if (err_status & XCAN_ESR_FMER_MASK) {
778 cf->can_id |= CAN_ERR_PROT;
779 cf->data[2] = CAN_ERR_PROT_FORM;
783 /* Check for CRC error interrupt */
784 if (err_status & XCAN_ESR_CRCER_MASK) {
787 cf->can_id |= CAN_ERR_PROT;
788 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
791 priv->can.can_stats.bus_error++;
796 stats->rx_bytes += cf->can_dlc;
800 netdev_dbg(ndev, "%s: error status register:0x%x\n",
801 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET));
805 * xcan_state_interrupt - It will check the state of the CAN device
806 * @ndev: net_device pointer
807 * @isr: interrupt status register value
809 * This will checks the state of the CAN device
810 * and puts the device into appropriate state.
812 static void xcan_state_interrupt(struct net_device *ndev, u32 isr)
814 struct xcan_priv *priv = netdev_priv(ndev);
816 /* Check for Sleep interrupt if set put CAN device in sleep state */
817 if (isr & XCAN_IXR_SLP_MASK)
818 priv->can.state = CAN_STATE_SLEEPING;
820 /* Check for Wake up interrupt if set put CAN device in Active state */
821 if (isr & XCAN_IXR_WKUP_MASK)
822 priv->can.state = CAN_STATE_ERROR_ACTIVE;
826 * xcan_rx_poll - Poll routine for rx packets (NAPI)
827 * @napi: napi structure pointer
828 * @quota: Max number of rx packets to be processed.
830 * This is the poll routine for rx part.
831 * It will process the packets maximux quota value.
833 * Return: number of packets received
835 static int xcan_rx_poll(struct napi_struct *napi, int quota)
837 struct net_device *ndev = napi->dev;
838 struct xcan_priv *priv = netdev_priv(ndev);
842 //netdev_warn(ndev, "DBG: xcan_rx_poll");
843 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
844 while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) {
845 //if (isr & XCAN_IXR_RXOK_MASK) {
846 priv->write_reg(priv, XCAN_ICR_OFFSET,
848 work_done += xcan_rx(ndev);
850 priv->write_reg(priv, XCAN_ICR_OFFSET,
851 XCAN_IXR_RXNEMP_MASK);
854 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK);
855 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
859 can_led_event(ndev, CAN_LED_EVENT_RX);
861 if (work_done < quota) {
863 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
864 ier |= (XCAN_IXR_RXOK_MASK | XCAN_IXR_RXNEMP_MASK);
865 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
871 * xcan_tx_interrupt - Tx Done Isr
872 * @ndev: net_device pointer
873 * @isr: Interrupt status register value
875 static void xcan_tx_interrupt(struct net_device *ndev, u32 isr)
877 struct xcan_priv *priv = netdev_priv(ndev);
878 struct net_device_stats *stats = &ndev->stats;
880 while ((priv->tx_head - priv->tx_tail > 0) &&
881 (isr & XCAN_IXR_TXOK_MASK)) {
882 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
883 can_get_echo_skb(ndev, priv->tx_tail %
887 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
889 can_led_event(ndev, CAN_LED_EVENT_TX);
890 netif_wake_queue(ndev);
894 * xcan_interrupt - CAN Isr
896 * @dev_id: device id poniter
898 * This is the xilinx CAN Isr. It checks for the type of interrupt
899 * and invokes the corresponding ISR.
902 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
904 static irqreturn_t xcan_interrupt(int irq, void *dev_id)
906 struct net_device *ndev = (struct net_device *)dev_id;
907 struct xcan_priv *priv = netdev_priv(ndev);
910 /* Get the interrupt status from Xilinx CAN */
911 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
912 //netdev_warn(ndev, "DBG: xcan_interrupt: ISR = 0x%08x, IER = 0x%08x", isr, priv->read_reg(priv, XCAN_IER_OFFSET));
916 /* Check for the type of interrupt and Processing it */
917 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) {
918 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |
919 XCAN_IXR_WKUP_MASK));
920 xcan_state_interrupt(ndev, isr);
923 /* Check for Tx interrupt and Processing it */
924 if (isr & XCAN_IXR_TXOK_MASK)
925 xcan_tx_interrupt(ndev, isr);
927 /* Check for the type of error interrupt and Processing it */
928 if (isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
929 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK)) {
930 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK |
931 XCAN_IXR_RXOFLW_MASK | XCAN_IXR_BSOFF_MASK |
932 XCAN_IXR_ARBLST_MASK));
933 xcan_err_interrupt(ndev, isr);
936 /* Check for the type of receive interrupt and Processing it */
937 if (isr & (XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK)) {
938 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
939 ier &= ~(XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK);
940 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
941 napi_schedule(&priv->napi);
947 * xcan_chip_stop - Driver stop routine
948 * @ndev: Pointer to net_device structure
950 * This is the drivers stop routine. It will disable the
951 * interrupts and put the device into configuration mode.
953 static void xcan_chip_stop(struct net_device *ndev)
955 struct xcan_priv *priv = netdev_priv(ndev);
958 /* Disable interrupts and leave the can in configuration mode */
959 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
960 ier &= ~XCAN_INTR_ALL;
961 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
962 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
963 priv->can.state = CAN_STATE_STOPPED;
967 * xcan_open - Driver open routine
968 * @ndev: Pointer to net_device structure
970 * This is the driver open routine.
971 * Return: 0 on success and failure value on error
973 static int xcan_open(struct net_device *ndev)
975 struct xcan_priv *priv = netdev_priv(ndev);
978 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
981 netdev_err(ndev, "irq allocation for CAN failed\n");
985 ret = clk_prepare_enable(priv->can_clk);
987 netdev_err(ndev, "unable to enable device clock\n");
991 ret = clk_prepare_enable(priv->bus_clk);
993 netdev_err(ndev, "unable to enable bus clock\n");
997 /* Set chip into reset mode */
998 ret = set_reset_mode(ndev);
1000 netdev_err(ndev, "mode resetting failed!\n");
1005 ret = open_candev(ndev);
1009 ret = xcan_chip_start(ndev);
1011 netdev_err(ndev, "xcan_chip_start failed!\n");
1015 can_led_event(ndev, CAN_LED_EVENT_OPEN);
1016 napi_enable(&priv->napi);
1017 netif_start_queue(ndev);
1024 clk_disable_unprepare(priv->bus_clk);
1026 clk_disable_unprepare(priv->can_clk);
1028 free_irq(ndev->irq, ndev);
1034 * xcan_close - Driver close routine
1035 * @ndev: Pointer to net_device structure
1039 static int xcan_close(struct net_device *ndev)
1041 struct xcan_priv *priv = netdev_priv(ndev);
1043 netif_stop_queue(ndev);
1044 napi_disable(&priv->napi);
1045 xcan_chip_stop(ndev);
1046 clk_disable_unprepare(priv->bus_clk);
1047 clk_disable_unprepare(priv->can_clk);
1048 free_irq(ndev->irq, ndev);
1051 can_led_event(ndev, CAN_LED_EVENT_STOP);
1057 * xcan_get_berr_counter - error counter routine
1058 * @ndev: Pointer to net_device structure
1059 * @bec: Pointer to can_berr_counter structure
1061 * This is the driver error counter routine.
1062 * Return: 0 on success and failure value on error
1064 static int xcan_get_berr_counter(const struct net_device *ndev,
1065 struct can_berr_counter *bec)
1067 struct xcan_priv *priv = netdev_priv(ndev);
1070 ret = clk_prepare_enable(priv->can_clk);
1074 ret = clk_prepare_enable(priv->bus_clk);
1078 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
1079 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
1080 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
1082 clk_disable_unprepare(priv->bus_clk);
1083 clk_disable_unprepare(priv->can_clk);
1088 clk_disable_unprepare(priv->can_clk);
1093 static int xcan_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1095 //struct xcan_priv *priv = netdev_priv(dev);
1096 struct hwtstamp_config cfg;
1098 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1101 /* reserved for future extensions */
1105 if (cfg.tx_type != HWTSTAMP_TX_OFF)
1108 switch (cfg.rx_filter) {
1109 case HWTSTAMP_FILTER_NONE:
1110 //priv->rx_enable = 0;
1112 case HWTSTAMP_FILTER_ALL:
1113 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1114 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1115 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1116 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1117 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1118 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1119 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1120 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1121 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1122 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1123 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1124 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1125 //priv->rx_enable = 1;
1126 cfg.rx_filter = HWTSTAMP_FILTER_ALL;
1132 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1135 static int xcan_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1137 //struct xcan_priv *priv = netdev_priv(dev);
1138 struct hwtstamp_config cfg;
1141 cfg.tx_type = HWTSTAMP_TX_OFF;
1142 cfg.rx_filter = //(xcan->rx_enable ?
1143 HWTSTAMP_FILTER_ALL;// : HWTSTAMP_FILTER_NONE);
1145 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1148 static int xcan_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1153 return xcan_hwtstamp_set(dev, ifr);
1155 return xcan_hwtstamp_get(dev, ifr);
1161 static const struct net_device_ops xcan_netdev_ops = {
1162 .ndo_open = xcan_open,
1163 .ndo_stop = xcan_close,
1164 .ndo_start_xmit = xcan_start_xmit,
1165 .ndo_change_mtu = can_change_mtu,
1166 .ndo_do_ioctl = xcan_ioctl,
1170 * xcan_suspend - Suspend method for the driver
1171 * @dev: Address of the platform_device structure
1173 * Put the driver into low power mode.
1176 static int __maybe_unused xcan_suspend(struct device *dev)
1178 struct platform_device *pdev = dev_get_drvdata(dev);
1179 struct net_device *ndev = platform_get_drvdata(pdev);
1180 struct xcan_priv *priv = netdev_priv(ndev);
1182 if (netif_running(ndev)) {
1183 netif_stop_queue(ndev);
1184 netif_device_detach(ndev);
1187 priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK);
1188 priv->can.state = CAN_STATE_SLEEPING;
1190 clk_disable(priv->bus_clk);
1191 clk_disable(priv->can_clk);
1197 * xcan_resume - Resume from suspend
1198 * @dev: Address of the platformdevice structure
1200 * Resume operation after suspend.
1201 * Return: 0 on success and failure value on error
1203 static int __maybe_unused xcan_resume(struct device *dev)
1205 struct platform_device *pdev = dev_get_drvdata(dev);
1206 struct net_device *ndev = platform_get_drvdata(pdev);
1207 struct xcan_priv *priv = netdev_priv(ndev);
1210 ret = clk_enable(priv->bus_clk);
1212 dev_err(dev, "Cannot enable clock.\n");
1215 ret = clk_enable(priv->can_clk);
1217 dev_err(dev, "Cannot enable clock.\n");
1218 clk_disable_unprepare(priv->bus_clk);
1222 priv->write_reg(priv, XCAN_MSR_OFFSET, 0);
1223 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
1224 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1226 if (netif_running(ndev)) {
1227 netif_device_attach(ndev);
1228 netif_start_queue(ndev);
1234 static SIMPLE_DEV_PM_OPS(xcan_dev_pm_ops, xcan_suspend, xcan_resume);
1237 * xcan_probe - Platform registration call
1238 * @pdev: Handle to the platform device structure
1240 * This function does all the memory allocation and registration for the CAN
1243 * Return: 0 on success and failure value on error
1245 static int xcan_probe(struct platform_device *pdev)
1247 struct resource *res; /* IO mem resources */
1248 struct net_device *ndev;
1249 struct xcan_priv *priv;
1251 int ret, rx_max, tx_max;
1253 /* Get the virtual base address for the device */
1254 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1255 addr = devm_ioremap_resource(&pdev->dev, res);
1257 ret = PTR_ERR(addr);
1261 ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", &tx_max);
1265 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", &rx_max);
1269 /* Create a CAN device instance */
1270 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max);
1274 priv = netdev_priv(ndev);
1276 priv->can.bittiming_const = &xcan_bittiming_const;
1277 priv->can.do_set_mode = xcan_do_set_mode;
1278 priv->can.do_get_berr_counter = xcan_get_berr_counter;
1279 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1280 CAN_CTRLMODE_BERR_REPORTING;
1281 priv->reg_base = addr;
1282 priv->tx_max = tx_max;
1284 /* Get IRQ for the device */
1285 ndev->irq = platform_get_irq(pdev, 0);
1286 ndev->flags |= IFF_ECHO; /* We support local echo */
1288 platform_set_drvdata(pdev, ndev);
1289 SET_NETDEV_DEV(ndev, &pdev->dev);
1290 ndev->netdev_ops = &xcan_netdev_ops;
1292 /* Getting the CAN can_clk info */
1293 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1294 if (IS_ERR(priv->can_clk)) {
1295 dev_err(&pdev->dev, "Device clock not found.\n");
1296 ret = PTR_ERR(priv->can_clk);
1299 /* Check for type of CAN device */
1300 if (of_device_is_compatible(pdev->dev.of_node,
1301 "xlnx,zynq-can-1.0")) {
1302 priv->bus_clk = devm_clk_get(&pdev->dev, "pclk");
1303 if (IS_ERR(priv->bus_clk)) {
1304 dev_err(&pdev->dev, "bus clock not found\n");
1305 ret = PTR_ERR(priv->bus_clk);
1309 priv->bus_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
1310 if (IS_ERR(priv->bus_clk)) {
1311 dev_err(&pdev->dev, "bus clock not found\n");
1312 ret = PTR_ERR(priv->bus_clk);
1317 ret = clk_prepare_enable(priv->can_clk);
1319 dev_err(&pdev->dev, "unable to enable device clock\n");
1323 ret = clk_prepare_enable(priv->bus_clk);
1325 dev_err(&pdev->dev, "unable to enable bus clock\n");
1326 goto err_unprepare_disable_dev;
1329 priv->write_reg = xcan_write_reg_le;
1330 priv->read_reg = xcan_read_reg_le;
1332 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {
1333 priv->write_reg = xcan_write_reg_be;
1334 priv->read_reg = xcan_read_reg_be;
1337 priv->can.clock.freq = clk_get_rate(priv->can_clk);
1339 netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max);
1341 ret = register_candev(ndev);
1343 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret);
1344 goto err_unprepare_disable_busclk;
1347 devm_can_led_init(ndev);
1348 clk_disable_unprepare(priv->bus_clk);
1349 clk_disable_unprepare(priv->can_clk);
1350 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n",
1351 priv->reg_base, ndev->irq, priv->can.clock.freq,
1354 priv->cantime2ns_shr = 0;
1355 priv->cantime2ns_mul = 1000000000U / priv->can.clock.freq;
1356 priv->ns2cantime_shr = 20;
1357 priv->ns2cantime_mul = div_u64((u64)priv->can.clock.freq << priv->ns2cantime_shr, 1000000000U);
1359 netdev_warn(ndev, "cantime2ns_mul = %u, cantime2ns_shr = %u, ns2cantime_mul = %u, ns2cantime_shr = %u",
1360 priv->cantime2ns_mul, priv->cantime2ns_shr, priv->ns2cantime_mul, priv->ns2cantime_shr);
1364 err_unprepare_disable_busclk:
1365 clk_disable_unprepare(priv->bus_clk);
1366 err_unprepare_disable_dev:
1367 clk_disable_unprepare(priv->can_clk);
1375 * xcan_remove - Unregister the device after releasing the resources
1376 * @pdev: Handle to the platform device structure
1378 * This function frees all the resources allocated to the device.
1381 static int xcan_remove(struct platform_device *pdev)
1383 struct net_device *ndev = platform_get_drvdata(pdev);
1384 struct xcan_priv *priv = netdev_priv(ndev);
1386 if (set_reset_mode(ndev) < 0)
1387 netdev_err(ndev, "mode resetting failed!\n");
1389 unregister_candev(ndev);
1390 netif_napi_del(&priv->napi);
1396 /* Match table for OF platform binding */
1397 static const struct of_device_id xcan_of_match[] = {
1398 { .compatible = "xlnx,zynq-can-1.0", },
1399 { .compatible = "xlnx,axi-can-1.00.a", },
1400 { /* end of list */ },
1402 MODULE_DEVICE_TABLE(of, xcan_of_match);
1404 static struct platform_driver xcan_driver = {
1405 .probe = xcan_probe,
1406 .remove = xcan_remove,
1408 .name = DRIVER_NAME,
1409 .pm = &xcan_dev_pm_ops,
1410 .of_match_table = xcan_of_match,
1414 module_platform_driver(xcan_driver);
1416 MODULE_LICENSE("GPL");
1417 MODULE_AUTHOR("Xilinx Inc");
1418 MODULE_DESCRIPTION("Xilinx CAN interface");