system/ip/can_crossbar_1.0/component.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
   3   <spirit:vendor>user.org</spirit:vendor>
   4   <spirit:library>user</spirit:library>
   5   <spirit:name>can_crossbar</spirit:name>
   6   <spirit:version>1.0</spirit:version>
   7   <spirit:busInterfaces>
   8     <spirit:busInterface>
   9       <spirit:name>S00_AXI</spirit:name>
  10       <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
  11       <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
  12       <spirit:slave>
  13         <spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
  14       </spirit:slave>
  15       <spirit:portMaps>
  16         <spirit:portMap>
  17           <spirit:logicalPort>
  18             <spirit:name>AWADDR</spirit:name>
  19           </spirit:logicalPort>
  20           <spirit:physicalPort>
  21             <spirit:name>s00_axi_awaddr</spirit:name>
  22           </spirit:physicalPort>
  23         </spirit:portMap>
  24         <spirit:portMap>
  25           <spirit:logicalPort>
  26             <spirit:name>AWPROT</spirit:name>
  27           </spirit:logicalPort>
  28           <spirit:physicalPort>
  29             <spirit:name>s00_axi_awprot</spirit:name>
  30           </spirit:physicalPort>
  31         </spirit:portMap>
  32         <spirit:portMap>
  33           <spirit:logicalPort>
  34             <spirit:name>AWVALID</spirit:name>
  35           </spirit:logicalPort>
  36           <spirit:physicalPort>
  37             <spirit:name>s00_axi_awvalid</spirit:name>
  38           </spirit:physicalPort>
  39         </spirit:portMap>
  40         <spirit:portMap>
  41           <spirit:logicalPort>
  42             <spirit:name>AWREADY</spirit:name>
  43           </spirit:logicalPort>
  44           <spirit:physicalPort>
  45             <spirit:name>s00_axi_awready</spirit:name>
  46           </spirit:physicalPort>
  47         </spirit:portMap>
  48         <spirit:portMap>
  49           <spirit:logicalPort>
  50             <spirit:name>WDATA</spirit:name>
  51           </spirit:logicalPort>
  52           <spirit:physicalPort>
  53             <spirit:name>s00_axi_wdata</spirit:name>
  54           </spirit:physicalPort>
  55         </spirit:portMap>
  56         <spirit:portMap>
  57           <spirit:logicalPort>
  58             <spirit:name>WSTRB</spirit:name>
  59           </spirit:logicalPort>
  60           <spirit:physicalPort>
  61             <spirit:name>s00_axi_wstrb</spirit:name>
  62           </spirit:physicalPort>
  63         </spirit:portMap>
  64         <spirit:portMap>
  65           <spirit:logicalPort>
  66             <spirit:name>WVALID</spirit:name>
  67           </spirit:logicalPort>
  68           <spirit:physicalPort>
  69             <spirit:name>s00_axi_wvalid</spirit:name>
  70           </spirit:physicalPort>
  71         </spirit:portMap>
  72         <spirit:portMap>
  73           <spirit:logicalPort>
  74             <spirit:name>WREADY</spirit:name>
  75           </spirit:logicalPort>
  76           <spirit:physicalPort>
  77             <spirit:name>s00_axi_wready</spirit:name>
  78           </spirit:physicalPort>
  79         </spirit:portMap>
  80         <spirit:portMap>
  81           <spirit:logicalPort>
  82             <spirit:name>BRESP</spirit:name>
  83           </spirit:logicalPort>
  84           <spirit:physicalPort>
  85             <spirit:name>s00_axi_bresp</spirit:name>
  86           </spirit:physicalPort>
  87         </spirit:portMap>
  88         <spirit:portMap>
  89           <spirit:logicalPort>
  90             <spirit:name>BVALID</spirit:name>
  91           </spirit:logicalPort>
  92           <spirit:physicalPort>
  93             <spirit:name>s00_axi_bvalid</spirit:name>
  94           </spirit:physicalPort>
  95         </spirit:portMap>
  96         <spirit:portMap>
  97           <spirit:logicalPort>
  98             <spirit:name>BREADY</spirit:name>
  99           </spirit:logicalPort>
 100           <spirit:physicalPort>
 101             <spirit:name>s00_axi_bready</spirit:name>
 102           </spirit:physicalPort>
 103         </spirit:portMap>
 104         <spirit:portMap>
 105           <spirit:logicalPort>
 106             <spirit:name>ARADDR</spirit:name>
 107           </spirit:logicalPort>
 108           <spirit:physicalPort>
 109             <spirit:name>s00_axi_araddr</spirit:name>
 110           </spirit:physicalPort>
 111         </spirit:portMap>
 112         <spirit:portMap>
 113           <spirit:logicalPort>
 114             <spirit:name>ARPROT</spirit:name>
 115           </spirit:logicalPort>
 116           <spirit:physicalPort>
 117             <spirit:name>s00_axi_arprot</spirit:name>
 118           </spirit:physicalPort>
 119         </spirit:portMap>
 120         <spirit:portMap>
 121           <spirit:logicalPort>
 122             <spirit:name>ARVALID</spirit:name>
 123           </spirit:logicalPort>
 124           <spirit:physicalPort>
 125             <spirit:name>s00_axi_arvalid</spirit:name>
 126           </spirit:physicalPort>
 127         </spirit:portMap>
 128         <spirit:portMap>
 129           <spirit:logicalPort>
 130             <spirit:name>ARREADY</spirit:name>
 131           </spirit:logicalPort>
 132           <spirit:physicalPort>
 133             <spirit:name>s00_axi_arready</spirit:name>
 134           </spirit:physicalPort>
 135         </spirit:portMap>
 136         <spirit:portMap>
 137           <spirit:logicalPort>
 138             <spirit:name>RDATA</spirit:name>
 139           </spirit:logicalPort>
 140           <spirit:physicalPort>
 141             <spirit:name>s00_axi_rdata</spirit:name>
 142           </spirit:physicalPort>
 143         </spirit:portMap>
 144         <spirit:portMap>
 145           <spirit:logicalPort>
 146             <spirit:name>RRESP</spirit:name>
 147           </spirit:logicalPort>
 148           <spirit:physicalPort>
 149             <spirit:name>s00_axi_rresp</spirit:name>
 150           </spirit:physicalPort>
 151         </spirit:portMap>
 152         <spirit:portMap>
 153           <spirit:logicalPort>
 154             <spirit:name>RVALID</spirit:name>
 155           </spirit:logicalPort>
 156           <spirit:physicalPort>
 157             <spirit:name>s00_axi_rvalid</spirit:name>
 158           </spirit:physicalPort>
 159         </spirit:portMap>
 160         <spirit:portMap>
 161           <spirit:logicalPort>
 162             <spirit:name>RREADY</spirit:name>
 163           </spirit:logicalPort>
 164           <spirit:physicalPort>
 165             <spirit:name>s00_axi_rready</spirit:name>
 166           </spirit:physicalPort>
 167         </spirit:portMap>
 168       </spirit:portMaps>
 169       <spirit:parameters>
 170         <spirit:parameter>
 171           <spirit:name>WIZ_DATA_WIDTH</spirit:name>
 172           <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
 173         </spirit:parameter>
 174         <spirit:parameter>
 175           <spirit:name>WIZ_NUM_REG</spirit:name>
 176           <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">4</spirit:value>
 177         </spirit:parameter>
 178         <spirit:parameter>
 179           <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
 180           <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
 181         </spirit:parameter>
 182       </spirit:parameters>
 183     </spirit:busInterface>
 184     <spirit:busInterface>
 185       <spirit:name>S00_AXI_RST</spirit:name>
 186       <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
 187       <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
 188       <spirit:slave/>
 189       <spirit:portMaps>
 190         <spirit:portMap>
 191           <spirit:logicalPort>
 192             <spirit:name>RST</spirit:name>
 193           </spirit:logicalPort>
 194           <spirit:physicalPort>
 195             <spirit:name>s00_axi_aresetn</spirit:name>
 196           </spirit:physicalPort>
 197         </spirit:portMap>
 198       </spirit:portMaps>
 199       <spirit:parameters>
 200         <spirit:parameter>
 201           <spirit:name>POLARITY</spirit:name>
 202           <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY">ACTIVE_LOW</spirit:value>
 203         </spirit:parameter>
 204       </spirit:parameters>
 205     </spirit:busInterface>
 206     <spirit:busInterface>
 207       <spirit:name>S00_AXI_CLK</spirit:name>
 208       <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
 209       <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
 210       <spirit:slave/>
 211       <spirit:portMaps>
 212         <spirit:portMap>
 213           <spirit:logicalPort>
 214             <spirit:name>CLK</spirit:name>
 215           </spirit:logicalPort>
 216           <spirit:physicalPort>
 217             <spirit:name>s00_axi_aclk</spirit:name>
 218           </spirit:physicalPort>
 219         </spirit:portMap>
 220       </spirit:portMaps>
 221       <spirit:parameters>
 222         <spirit:parameter>
 223           <spirit:name>ASSOCIATED_BUSIF</spirit:name>
 224           <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
 225         </spirit:parameter>
 226         <spirit:parameter>
 227           <spirit:name>ASSOCIATED_RESET</spirit:name>
 228           <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
 229         </spirit:parameter>
 230       </spirit:parameters>
 231     </spirit:busInterface>
 232   </spirit:busInterfaces>
 233   <spirit:memoryMaps>
 234     <spirit:memoryMap>
 235       <spirit:name>S00_AXI</spirit:name>
 236       <spirit:addressBlock>
 237         <spirit:name>S00_AXI_reg</spirit:name>
 238         <spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
 239         <spirit:range spirit:format="long">4096</spirit:range>
 240         <spirit:width spirit:format="long">32</spirit:width>
 241         <spirit:usage>register</spirit:usage>
 242         <spirit:parameters>
 243           <spirit:parameter>
 244             <spirit:name>OFFSET_BASE_PARAM</spirit:name>
 245             <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
 246           </spirit:parameter>
 247           <spirit:parameter>
 248             <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
 249             <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
 250           </spirit:parameter>
 251         </spirit:parameters>
 252       </spirit:addressBlock>
 253     </spirit:memoryMap>
 254   </spirit:memoryMaps>
 255   <spirit:model>
 256     <spirit:views>
 257       <spirit:view>
 258         <spirit:name>xilinx_verilogsynthesis</spirit:name>
 259         <spirit:displayName>Verilog Synthesis</spirit:displayName>
 260         <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
 261         <spirit:language>verilog</spirit:language>
 262         <spirit:modelName>can_crossbar_v1_0</spirit:modelName>
 263         <spirit:fileSetRef>
 264           <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
 265         </spirit:fileSetRef>
 266         <spirit:parameters>
 267           <spirit:parameter>
 268             <spirit:name>viewChecksum</spirit:name>
 269             <spirit:value>73ee1312</spirit:value>
 270           </spirit:parameter>
 271         </spirit:parameters>
 272       </spirit:view>
 273       <spirit:view>
 274         <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
 275         <spirit:displayName>Verilog Simulation</spirit:displayName>
 276         <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
 277         <spirit:language>verilog</spirit:language>
 278         <spirit:modelName>can_crossbar_v1_0</spirit:modelName>
 279         <spirit:fileSetRef>
 280           <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
 281         </spirit:fileSetRef>
 282         <spirit:parameters>
 283           <spirit:parameter>
 284             <spirit:name>viewChecksum</spirit:name>
 285             <spirit:value>73ee1312</spirit:value>
 286           </spirit:parameter>
 287         </spirit:parameters>
 288       </spirit:view>
 289       <spirit:view>
 290         <spirit:name>xilinx_softwaredriver</spirit:name>
 291         <spirit:displayName>Software Driver</spirit:displayName>
 292         <spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
 293         <spirit:fileSetRef>
 294           <spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
 295         </spirit:fileSetRef>
 296         <spirit:parameters>
 297           <spirit:parameter>
 298             <spirit:name>viewChecksum</spirit:name>
 299             <spirit:value>f1bf0c25</spirit:value>
 300           </spirit:parameter>
 301         </spirit:parameters>
 302       </spirit:view>
 303       <spirit:view>
 304         <spirit:name>xilinx_xpgui</spirit:name>
 305         <spirit:displayName>UI Layout</spirit:displayName>
 306         <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
 307         <spirit:fileSetRef>
 308           <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
 309         </spirit:fileSetRef>
 310         <spirit:parameters>
 311           <spirit:parameter>
 312             <spirit:name>viewChecksum</spirit:name>
 313             <spirit:value>fd592ead</spirit:value>
 314           </spirit:parameter>
 315         </spirit:parameters>
 316       </spirit:view>
 317       <spirit:view>
 318         <spirit:name>bd_tcl</spirit:name>
 319         <spirit:displayName>Block Diagram</spirit:displayName>
 320         <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
 321         <spirit:fileSetRef>
 322           <spirit:localName>bd_tcl_view_fileset</spirit:localName>
 323         </spirit:fileSetRef>
 324         <spirit:parameters>
 325           <spirit:parameter>
 326             <spirit:name>viewChecksum</spirit:name>
 327             <spirit:value>45a2f450</spirit:value>
 328           </spirit:parameter>
 329         </spirit:parameters>
 330       </spirit:view>
 331     </spirit:views>
 332     <spirit:ports>
 333       <spirit:port>
 334         <spirit:name>can1_rx</spirit:name>
 335         <spirit:wire>
 336           <spirit:direction>in</spirit:direction>
 337           <spirit:wireTypeDefs>
 338             <spirit:wireTypeDef>
 339               <spirit:typeName>wire</spirit:typeName>
 340               <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
 341               <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
 342             </spirit:wireTypeDef>
 343           </spirit:wireTypeDefs>
 344         </spirit:wire>
 345       </spirit:port>
 346       <spirit:port>
 347         <spirit:name>can2_rx</spirit:name>
 348         <spirit:wire>
 349           <spirit:direction>in</spirit:direction>
 350           <spirit:wireTypeDefs>
 351             <spirit:wireTypeDef>
 352               <spirit:typeName>wire</spirit:typeName>
 353               <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
 354               <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
 355             </spirit:wireTypeDef>
 356           </spirit:wireTypeDefs>
 357         </spirit:wire>
 358       </spirit:port>
 359       <spirit:port>
 360         <spirit:name>can3_rx</spirit:name>
 361         <spirit:wire>
 362           <spirit:direction>in</spirit:direction>
 363           <spirit:wireTypeDefs>
 364             <spirit:wireTypeDef>
 365               <spirit:typeName>wire</spirit:typeName>
 366               <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
 367               <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
 368             </spirit:wireTypeDef>
 369           </spirit:wireTypeDefs>
 370         </spirit:wire>
 371       </spirit:port>
 372       <spirit:port>
 373         <spirit:name>can4_rx</spirit:name>
 374         <spirit:wire>
 375           <spirit:direction>in</spirit:direction>
 376           <spirit:wireTypeDefs>
 377             <spirit:wireTypeDef>
 378               <spirit:typeName>wire</spirit:typeName>
 379               <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
 380               <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
 381             </spirit:wireTypeDef>
 382           </spirit:wireTypeDefs>
 383         </spirit:wire>
 384       </spirit:port>
 385       <spirit:port>
 386         <spirit:name>can1_tx</spirit:name>
 387         <spirit:wire>
 388           <spirit:direction>out</spirit:direction>
 389           <spirit:wireTypeDefs>
 390             <spirit:wireTypeDef>
 391               <spirit:typeName>wire</spirit:typeName>
 392               <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
 393               <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
 394             </spirit:wireTypeDef>
 395           </spirit:wireTypeDefs>
 396         </spirit:wire>
 397       </spirit:port>
 398       <spirit:port>
 399         <spirit:name>can2_tx</spirit:name>
 400         <spirit:wire>
 401           <spirit:direction>out</spirit:direction>
 402           <spirit:wireTypeDefs>
 403             <spirit:wireTypeDef>
 404               <spirit:typeName>wire</spirit:typeName>
 405               <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
 406               <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
 407             </spirit:wireTypeDef>
 408           </spirit:wireTypeDefs>
 409         </spirit:wire>
 410       </spirit:port>
 411       <spirit:port>
 412         <spirit:name>can3_tx</spirit:name>
 413         <spirit:wire>
 414           <spirit:direction>out</spirit:direction>
 415           <spirit:wireTypeDefs>
 416             <spirit:wireTypeDef>
 417               <spirit:typeName>wire</spirit:typeName>
 418               <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
 419               <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
 420             </spirit:wireTypeDef>
 421           </spirit:wireTypeDefs>
 422         </spirit:wire>
 423       </spirit:port>
 424       <spirit:port>
 425         <spirit:name>can4_tx</spirit:name>
 426         <spirit:wire>
 427           <spirit:direction>out</spirit:direction>
 428           <spirit:wireTypeDefs>
 429             <spirit:wireTypeDef>
 430               <spirit:typeName>wire</spirit:typeName>
 431               <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
 432               <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
 433             </spirit:wireTypeDef>
 434           </spirit:wireTypeDefs>
 435         </spirit:wire>
 436       </spirit:port>
 437       <spirit:port>
 438         <spirit:name>ifc1_tx</spirit:name>
 439         <spirit:wire>
 440           <spirit:direction>in</spirit:direction>
 441           <spirit:wireTypeDefs>
 442             <spirit:wireTypeDef>
 443               <spirit:typeName>wire</spirit:typeName>
 444               <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
 445               <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
 446             </spirit:wireTypeDef>
 447           </spirit:wireTypeDefs>
 448         </spirit:wire>
 449       </spirit:port>
 450       <spirit:port>
 451         <spirit:name>ifc2_tx</spirit:name>
 452         <spirit:wire>
 453           <spirit:direction>in</spirit:direction>
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 459             </spirit:wireTypeDef>
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 867         <spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
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