2 use IEEE.STD_LOGIC_1164.ALL;
4 -- Uncomment the following library declaration if using
5 -- arithmetic functions with Signed or Unsigned values
6 --use IEEE.NUMERIC_STD.ALL;
8 -- Uncomment the following library declaration if instantiating
9 -- any Xilinx leaf cells in this code.
11 --use UNISIM.VComponents.all;
14 Port ( can_rx : out STD_LOGIC;
15 can_tx1 : in STD_LOGIC := '1';
16 can_tx2 : in STD_LOGIC := '1';
17 can_tx3 : in STD_LOGIC := '1');
20 architecture Behavioral of can_merge is
22 can_rx <= can_tx1 and can_tx2 and can_tx3;