]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-hw.git/history - jx1.sch
power: LM2676, VCCIO reg FB divider changed, footprints, descriptions
[fpga/zynq/canbench-hw.git] / jx1.sch
2016-04-10 Martin Jerabekpower reg changed, I/O pin assignment, testpoints, CAN
2016-04-05 Martin JerabekCAN termination & merging redesigned, added connectors...
2016-03-15 Martin JerabekUsed MicroHeaders from kicad-parts