-# Net names are not allowed to contain hyphen characters '-' since this
-# is not a legal VHDL87 or Verilog character within an identifier.
-# HDL net names are adjusted to contain no hyphen characters '-' but
-# rather use underscore '_' characters. Comment net name with the hyphen
-# characters will remain in place since these are intended to match the
-# schematic net names in order to better enable schematic search.
-#
-# ----------------------------------------------------------------------------
-
-
-# Warning: This is not up to date!
-# Will update after the assignment is fixed ...
-error!
-
-# ------------------------------------------------------------------------------
-# User LEDs (Bank 34)
-# ------------------------------------------------------------------------------
-set_property PACKAGE_PIN T11 [get_ports {LED1}]; # JX1_LVDS_0_P
-set_property PACKAGE_PIN T10 [get_ports {LED2}]; # JX1_LVDS_0_N
-set_property PACKAGE_PIN U13 [get_ports {LED3}]; # JX1_LVDS_2_P
-set_property PACKAGE_PIN V13 [get_ports {LED4}]; # JX1_LVDS_2_N
-set_property PACKAGE_PIN T14 [get_ports {LED5}]; # JX1_LVDS_4_P
-set_property PACKAGE_PIN T15 [get_ports {LED6}]; # JX1_LVDS_4_N
-set_property PACKAGE_PIN Y16 [get_ports {LED7}]; # JX1_LVDS_6_P
-set_property PACKAGE_PIN Y17 [get_ports {LED8}]; # JX1_LVDS_6_N
-set_property DIRECTION OUT [get_ports [list LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8]]
-
-# ------------------------------------------------------------------------------
-# User KEYs (Bank 34)
-# ------------------------------------------------------------------------------
-set_property PACKAGE_PIN T16 [get_ports {KEY1}]; # JX1_LVDS_8_P
-set_property PACKAGE_PIN U17 [get_ports {KEY2}]; # JX1_LVDS_8_N
-set_property PACKAGE_PIN U14 [get_ports {KEY3}]; # JX1_LVDS_10_P
-set_property PACKAGE_PIN U15 [get_ports {KEY4}]; # JX1_LVDS_10_N
-set_property DIRECTION IN [get_ports [list KEY1 KEY2 KEY3 KEY4]]
-
-# ------------------------------------------------------------------------------
-# User DIP SWs (Bank 34)
-# ------------------------------------------------------------------------------
-set_property PACKAGE_PIN N18 [get_ports {SW1}]; # JX1_LVDS_12_P
-set_property PACKAGE_PIN P19 [get_ports {SW2}]; # JX1_LVDS_12_N
-set_property PACKAGE_PIN T20 [get_ports {SW3}]; # JX1_LVDS_14_P
-set_property PACKAGE_PIN U20 [get_ports {SW4}]; # JX1_LVDS_14_N
-set_property PACKAGE_PIN Y18 [get_ports {SW5}]; # JX1_LVDS_16_P
-set_property PACKAGE_PIN Y19 [get_ports {SW6}]; # JX1_LVDS_16_N
-set_property PACKAGE_PIN R16 [get_ports {SW7}]; # JX1_LVDS_18_P
-set_property PACKAGE_PIN R17 [get_ports {SW8}]; # JX1_LVDS_18_N
-set_property DIRECTION IN [get_ports [list SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8]]
-
-# ------------------------------------------------------------------------------
-# CAN interfaces (Bank 34)
-# ------------------------------------------------------------------------------
-set_property PACKAGE_PIN T12 [get_ports {CAN1_RXD}]; # JX1_LVDS_1_P
-set_property PACKAGE_PIN U12 [get_ports {CAN1_TXD}]; # JX1_LVDS_1_N
-set_property PACKAGE_PIN V12 [get_ports {CAN2_RXD}]; # JX1_LVDS_3_P
-set_property PACKAGE_PIN W13 [get_ports {CAN2_TXD}]; # JX1_LVDS_3_N
-set_property PACKAGE_PIN P14 [get_ports {CAN3_RXD}]; # JX1_LVDS_5_P
-set_property PACKAGE_PIN R14 [get_ports {CAN3_TXD}]; # JX1_LVDS_5_N
-set_property PACKAGE_PIN W14 [get_ports {CAN4_RXD}]; # JX1_LVDS_7_P
-set_property PACKAGE_PIN Y14 [get_ports {CAN4_TXD}]; # JX1_LVDS_7_N
-set_property PACKAGE_PIN T19 [get_ports {CAN_STBY}]; # JX1_SE_1
-
-set_property DIRECTION IN [get_ports [list CAN1_RXD CAN2_RXD CAN3_RXD CAN4_RXD ]]
-set_property DIRECTION OUT [get_ports [list CAN1_TXD CAN2_TXD CAN3_TXD CAN4_TXD CAN_STBY ]]
-
-
-#set_property PACKAGE_PIN U19 [get_ports {JX1_LVDS_11_N}];
-#set_property PACKAGE_PIN U18 [get_ports {JX1_LVDS_11_P}];
-#set_property PACKAGE_PIN P20 [get_ports {JX1_LVDS_13_N}];
-#set_property PACKAGE_PIN N20 [get_ports {JX1_LVDS_13_P}];
-#set_property PACKAGE_PIN W20 [get_ports {JX1_LVDS_15_N}];
-#set_property PACKAGE_PIN V20 [get_ports {JX1_LVDS_15_P}];
-#set_property PACKAGE_PIN W16 [get_ports {JX1_LVDS_17_N}];
-#set_property PACKAGE_PIN V16 [get_ports {JX1_LVDS_17_P}];
-#set_property PACKAGE_PIN R18 [get_ports {JX1_LVDS_19_N}];
-#set_property PACKAGE_PIN T17 [get_ports {JX1_LVDS_19_P}];
-#set_property PACKAGE_PIN V18 [get_ports {JX1_LVDS_20_N}];
-#set_property PACKAGE_PIN V17 [get_ports {JX1_LVDS_20_P}];
-#set_property PACKAGE_PIN W19 [get_ports {JX1_LVDS_21_N}];
-#set_property PACKAGE_PIN W18 [get_ports {JX1_LVDS_21_P}];
-#set_property PACKAGE_PIN P18 [get_ports {JX1_LVDS_22_N}];
-#set_property PACKAGE_PIN N17 [get_ports {JX1_LVDS_22_P}];
-#set_property PACKAGE_PIN P16 [get_ports {JX1_LVDS_23_N}];
-#set_property PACKAGE_PIN P15 [get_ports {JX1_LVDS_23_P}];
-#set_property PACKAGE_PIN W15 [get_ports {JX1_LVDS_9_N}];
-#set_property PACKAGE_PIN V15 [get_ports {JX1_LVDS_9_P}];
-#set_property PACKAGE_PIN R19 [get_ports {JX1_SE_0}];
-
-
-# ------------------------------------------------------------------------------
-# Screw terminal JX (Bank 35)
-# ------------------------------------------------------------------------------
-set_property PACKAGE_PIN C20 [get_ports {JX1}]; # JX2_LVDS_0_P
-set_property PACKAGE_PIN B20 [get_ports {JX2}]; # JX2_LVDS_0_N
-set_property PACKAGE_PIN E17 [get_ports {JX3}]; # JX2_LVDS_2_P
-set_property PACKAGE_PIN D18 [get_ports {JX4}]; # JX2_LVDS_2_N
-
-# ------------------------------------------------------------------------------
-# PMOD JA (Bank 35)
-# ------------------------------------------------------------------------------
-set_property PACKAGE_PIN E18 [get_ports {JA0_1_P}]; # JX2_LVDS_4_P JA Pin 1
-set_property PACKAGE_PIN E19 [get_ports {JA0_1_N}]; # JX2_LVDS_4_N JA Pin 2
-set_property PACKAGE_PIN L19 [get_ports {JA2_3_P}]; # JX2_LVDS_6_P JA Pin 3
-set_property PACKAGE_PIN L20 [get_ports {JA2_3_N}]; # JX2_LVDS_6_N JA Pin 4
-set_property PACKAGE_PIN M17 [get_ports {JA4_5_P}]; # JX2_LVDS_8_P JA Pin 7
-set_property PACKAGE_PIN M18 [get_ports {JA4_5_N}]; # JX2_LVDS_8_N JA Pin 8
-set_property PACKAGE_PIN L16 [get_ports {JA6_7_P}]; # JX2_LVDS_10_P JA Pin 9
-set_property PACKAGE_PIN L17 [get_ports {JA6_7_N}]; # JX2_LVDS_10_N JA Pin 10
-
-# ------------------------------------------------------------------------------
-# PMOD JB (Bank 35)
-# ------------------------------------------------------------------------------
-set_property PACKAGE_PIN B19 [get_ports {JB0_1_P}]; # JX2_LVDS_1_P JA Pin 1
-set_property PACKAGE_PIN A20 [get_ports {JB0_1_N}]; # JX2_LVDS_1_N JA Pin 2
-set_property PACKAGE_PIN D19 [get_ports {JB2_3_P}]; # JX2_LVDS_3_P JA Pin 3
-set_property PACKAGE_PIN D20 [get_ports {JB2_3_N}]; # JX2_LVDS_3_N JA Pin 4
-set_property PACKAGE_PIN F16 [get_ports {JB4_5_P}]; # JX2_LVDS_5_P JA Pin 7
-set_property PACKAGE_PIN F17 [get_ports {JB4_5_N}]; # JX2_LVDS_5_N JA Pin 8
-set_property PACKAGE_PIN M19 [get_ports {JB6_7_P}]; # JX2_LVDS_7_P JA Pin 9
-set_property PACKAGE_PIN M20 [get_ports {JB6_7_N}]; # JX2_LVDS_7_N JA Pin 10
-
-# ------------------------------------------------------------------------------
-# Raspberry Pi GPIO Header (Bank 35)
-# ------------------------------------------------------------------------------
-set_property PACKAGE_PIN K19 [get_ports {JP_GPIO2_SDA}]; # JX2_LVDS_9_P
-set_property PACKAGE_PIN J19 [get_ports {JP_GPIO3_SCL}]; # JX2_LVDS_9_N
-set_property PACKAGE_PIN K17 [get_ports {JP_GPIO4}]; # JX2_LVDS_11_P
-set_property PACKAGE_PIN K18 [get_ports {JP_GPIO17}]; # JX2_LVDS_11_N
-set_property PACKAGE_PIN J18 [get_ports {JP_GPIO27}]; # JX2_LVDS_13_P
-set_property PACKAGE_PIN H18 [get_ports {JP_GPIO22}]; # JX2_LVDS_13_N
-set_property PACKAGE_PIN F19 [get_ports {JP_GPIO10_MOSI}];# JX2_LVDS_15_P
-set_property PACKAGE_PIN F20 [get_ports {JP_GPIO9_MISO}]; # JX2_LVDS_15_N
-set_property PACKAGE_PIN J20 [get_ports {JP_GPIO11_SCLK}];# JX2_LVDS_17_P
-set_property PACKAGE_PIN H20 [get_ports {JP_ID_SD}]; # JX2_LVDS_17_N
-set_property PACKAGE_PIN H15 [get_ports {JP_GPIO5}]; # JX2_LVDS_19_P
-set_property PACKAGE_PIN G15 [get_ports {JP_GPIO6}]; # JX2_LVDS_19_N
-set_property PACKAGE_PIN L14 [get_ports {JP_GPIO13}]; # JX2_LVDS_21_P
-set_property PACKAGE_PIN L15 [get_ports {JP_GPIO19}]; # JX2_LVDS_21_N
-set_property PACKAGE_PIN H16 [get_ports {JP_GPIO14_TXD}]; # JX2_LVDS_12_P
-set_property PACKAGE_PIN H17 [get_ports {JP_GPIO15_RXD}]; # JX2_LVDS_12_N
-set_property PACKAGE_PIN G17 [get_ports {JP_GPIO18_PWM}]; # JX2_LVDS_14_P
-set_property PACKAGE_PIN G18 [get_ports {JP_GPIO23}]; # JX2_LVDS_14_N
-set_property PACKAGE_PIN G19 [get_ports {JP_GPIO24}]; # JX2_LVDS_16_P
-set_property PACKAGE_PIN G20 [get_ports {JP_GPIO25}]; # JX2_LVDS_16_N
-set_property PACKAGE_PIN K14 [get_ports {JP_GPIO8_CE0}]; # JX2_LVDS_18_P
-set_property PACKAGE_PIN J14 [get_ports {JP_GPIO7_CE1}]; # JX2_LVDS_18_N
-set_property PACKAGE_PIN N15 [get_ports {JP_ID_SC}]; # JX2_LVDS_20_P
-set_property PACKAGE_PIN N16 [get_ports {JP_GPIO12}]; # JX2_LVDS_20_N
-set_property PACKAGE_PIN M14 [get_ports {JP_GPIO16}]; # JX2_LVDS_22_P
-set_property PACKAGE_PIN M15 [get_ports {JP_GPIO20}]; # JX2_LVDS_22_N
-set_property PACKAGE_PIN K16 [get_ports {JP_GPIO26}]; # JX2_LVDS_23_P
-set_property PACKAGE_PIN J16 [get_ports {JP_GPIO21}]; # JX2_LVDS_23_N
-
-#set_property PACKAGE_PIN G14 [get_ports {JX2_SE_0}];
-#set_property PACKAGE_PIN J15 [get_ports {JX2_SE_1}];
-
-# Set the bank voltage for IO Bank 34 to 3.3V by default.
-set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
-
-# Set the bank voltage for IO Bank 35 to 3.3V by default.
-set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
projects / fpga / zynq / canbench-hw.git / commitdiff