layout: CAN, user LEDs, KEYs, SWs, JX2

[fpga/zynq/canbench-hw.git] / power.sch

diff --git a/power.sch b/power.sch
index 762b0b127cb974121ffcbc1a1ce2c4f5bd743ebc..8a0b11947f82b341a267e7a0ea72e3c8e79469ee 100644 (file)
--- a/power.sch
+++ b/power.sch
@@ -819,7 +819,7 @@ U 1 1 5712ED40
 P 1900 3650
 F 0 "JP1" H 1900 3730 50  0000 C CNN
 F 1 "Jumper_NO_Small" H 1910 3590 50  0001 C CNN
-F 2 "Pin_Headers:Pin_Header_Straight_1x02" H 1900 3650 50  0001 C CNN
+F 2 "footprints:Pin_Header_Straight_1x02" H 1900 3650 50  0001 C CNN
 F 3 "" H 1900 3650 50  0000 C CNN
        1    1900 3650
        -1   0    0    1   
@@ -1409,4 +1409,6 @@ F 3 "" H 1500 900 50  0000 C CNN
 $EndComp
 Wire Wire Line
        1750 1500 1750 1700
+Text Label 6750 1150 0    60   ~ 0
+LM2675_FB
 $EndSCHEMATC