layout: connectors, KEYs; added ESD protection

[fpga/zynq/canbench-hw.git] / power.sch

diff --git a/power.sch b/power.sch
index 762b0b127cb974121ffcbc1a1ce2c4f5bd743ebc..40b51989c884b6bfcb172d3089400062dccd16ac 100644 (file)
--- a/power.sch
+++ b/power.sch
@@ -77,6 +77,7 @@ LIBS:mcp
 LIBS:JX1
 LIBS:JX2
 LIBS:gates
+LIBS:usblc6
 LIBS:canbench-hw-cache
 EELAYER 25 0
 EELAYER END
@@ -819,7 +820,7 @@ U 1 1 5712ED40
 P 1900 3650
 F 0 "JP1" H 1900 3730 50  0000 C CNN
 F 1 "Jumper_NO_Small" H 1910 3590 50  0001 C CNN
-F 2 "Pin_Headers:Pin_Header_Straight_1x02" H 1900 3650 50  0001 C CNN
+F 2 "footprints:Pin_Header_Straight_1x02" H 1900 3650 50  0001 C CNN
 F 3 "" H 1900 3650 50  0000 C CNN
        1    1900 3650
        -1   0    0    1   
@@ -1409,4 +1410,6 @@ F 3 "" H 1500 900 50  0000 C CNN
 $EndComp
 Wire Wire Line
        1750 1500 1750 1700
+Text Label 6750 1150 0    60   ~ 0
+LM2675_FB
 $EndSCHEMATC