1 The following files were generated for 'rom_8x2k' in directory
5 Please see the core data sheet.
8 Text file listing all of the output files produced when a customized
9 core was generated in the CORE Generator.
12 Please see the core data sheet.
15 CORE Generator input file containing the parameters used to
19 VHO template file containing code that can be used as a model for
20 instantiating a CORE Generator module in a VHDL design.
23 Text file indicating the files generated and how they are used.
26 Graphical symbol information file. Used by the ISE tools and some
27 third party tools to create a symbol representing the core.
30 Binary Xilinx implementation netlist file containing the information
31 required to implement the module in a Xilinx (R) FPGA.
34 VHDL wrapper file provided to support functional simulation. This
35 file contains simulation model customization data that is passed to
36 a parameterized simulation model for the core.
39 Please see the Xilinx CORE Generator online help for further details on
40 generated files and how to use them.