]> rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/blob - coregen/rom_8x2k_flist.txt
projects / fpga / virtex2 / uart.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
+ README
[fpga/virtex2/uart.git] / coregen / rom_8x2k_flist.txt
1 # Output products list for <rom_8x2k>
2 rom_8x2k_xmdf.tcl
3 rom_8x2k_flist.txt
4 rom_8x2k.sym
5 rom_8x2k.xco
6 rom_8x2k.vho
7 rom_8x2k.asy
8 rom_8x2k.ngc
9 rom_8x2k.vhd
MSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board