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Connection of HW UART peripheral
[fpga/virtex2/uart.git] / software / fll.s
1 #include "hardware.h"
2 .text
3 .global fllInit                         ; SW FLL to init DCO/SMCLK -frequency
4         .type   fllInit, @function
5 fllInit:
6         mov.b   #BCSCTL1_FLL, &BCSCTL1  ; Init basic clock control reg 1
7         mov.b   #BCSCTL2_FLL, &BCSCTL2  ; Init basic clock control reg 2
8         mov     #TACTL_FLL, &TACTL      ; SMCLK is TA-clock / Timer stopped
9         bis     #MC1, &TACTL            ; Start timer: Continuos Mode
10         mov     #CCTL2_FLL, &CCTL2      ; Init CCR2 and Clear capture flag
11
12 .Lwait0:bit     #CCIFG, &CCTL2          ; Test/Wait for capture flag
13         jz      .Lwait0                 ; May be used with INT / LPM0 later ?
14         mov     &CCR2, r15              ; Store CCR2 init-value
15         bic     #CCIFG, &CCTL2          ; Clear capture flag
16 .Lwait1:bit     #CCIFG, &CCTL2          ; Test/Wait for capture flag
17         jz      .Lwait1                 ; May be used with INT / LPM0 later ?
18         bic     #CCIFG, &CCTL2          ; Clear capture flag
19         mov.b   &BCSCTL1, r14           ; Store current Rsel value
20         bic.b   #0x0f8, r14             ; Mask for Rsel bits
21         mov.b   &DCOCTL, r13            ; Store current DCO value
22
23 .LfllUP:cmp.b   #DCOCTL_MAX, r13        ; Needs Rsel to be increased ?
24         jne     .LfllDN                 ; No
25         cmp.b   #7, r14                 ; Is max Rsel already selected ?
26         jge     .LfllER                 ; Yes, Rsel can not be increased
27         inc.b   &BCSCTL1                ; Increase Rsel
28         jmp     .LfllRx                 ; Test DCO again
29
30 .LfllDN:cmp.b   #DCOCTL_MIN, r13        ; Needs Rsel to be decreased ?
31         jne     .LfllCP                 ; No
32         cmp.b   #0, r14                 ; Is min Rsel already selected ?
33         jeq     .LfllER                 ; Yes, Rsel can not be increased
34         dec.b   &BCSCTL1                ; Decrease Rsel
35 .LfllRx:mov.b   #60h, &DCOCTL           ; Center DCO (may be optimized later ?)
36         jmp     .Lwait0                 ; Test DCO again
37 .LfllCP:
38         mov     &CCR2, r12              ; Read captured value
39         sub     r15, r12                ; Subtract last captured value
40         mov     &CCR2, r15              ; Store CCR2 value for next pass
41         cmp     #DCO_FSET, r12          ; DCO_FSET= SMCLK/(32768/4)
42         jl      .LfllI                  ;
43         jeq     .LfllOK                 ;
44 .LfllD: dec.b   &DCOCTL                 ; Decrement value
45         jmp     .Lwait0                 ;
46 .LfllI: inc.b   &DCOCTL                 ; Increment value
47         jmp     .Lwait0                 ;
48
49 .LfllER:                                ; error, currently ingnored
50 .LfllOK:clr     &CCTL2                  ; stop CCR2
51         ret                             ;