From dea7f319282d48c6279e4764ce66bcf0318f2cb7 Mon Sep 17 00:00:00 2001 From: Vladimir Burian Date: Wed, 18 May 2011 23:48:36 +0200 Subject: [PATCH] PWM output polarity inverted. Inverted to correspond with power electronic board LP_MPW1 where PWM input signals are inverted too. --- msp_motion.vhd | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/msp_motion.vhd b/msp_motion.vhd index b131d18..a976948 100644 --- a/msp_motion.vhd +++ b/msp_motion.vhd @@ -417,12 +417,13 @@ begin pwm => PWM3_OUT); -- PWM signals mapped to FPGA outputs, EN forced to '1' - PWM0 <= PWM1_OUT; + PWM0 <= not PWM1_OUT; PWM0_EN <= '1'; - PWM1 <= PWM2_OUT; + PWM1 <= not PWM2_OUT; PWM1_EN <= '1'; - PWM2 <= PWM3_OUT; + PWM2 <= not PWM3_OUT; PWM2_EN <= '1'; + -- PWM is signalized on LEDs LED0 <= PWM1_OUT; LED1 <= PWM2_OUT; -- 2.39.2