Whole "make process" with use of ISE project

[fpga/virtex2/msp_motion.git] / build / Makefile

diff --git a/build/Makefile b/build/Makefile
index 943fb60ba1b2d57a095fd87cab66c25cbaba3e51..68edd3b6d01fa9332ffc8172f04c675708926404 100644 (file)
--- a/build/Makefile
+++ b/build/Makefile
@@ -1,14 +1,10 @@
 # TOP           - Name of the top-level module
-# DEVICE        - Name of the FPGA device (device-package-speed)
 # PRJ           - Name of .prj file with names of all source files. See XST manual.
 # UCF           - Name of the user constraints file
 # BMM           - If design contains initialized memories, softcore MCU, etc., this
 #                 file describes mapping of .elf file to these memories. Only one
 #                 .bmm file can be used.
-# SEARCH_DIRS   - Directories to search when searching for netlists (.ngc, ...).
-#                 See NGDBUILD manual.
 # JTAG_POS      - Position of device in JTAG chain. Used when downloading bit stream.
-# INTSTYLE      - Style of screen output. (ise | xflow | silent)
 # SRC           - Path to the source directory. All other paths are relative to this.
 
 # Makefile is interconnected with Ocera-makefile system by the following properties
@@ -30,28 +26,27 @@
 #                 and type 'help'.
 #  - synthesize : Synthesize all VHDL and Verilog source files, libraries, etc.
 #                 defined in PRJ files and produces NGC file.
-#  - translate  : Translate all netlist files (.ngc, ...) into the NGD file,
+#  - implment   : Translate all netlist files (.ngc, ...) into the NGD file,
 #                 where the design is described in terms of deneral logic elements
 #                 such as (RAM, flip-flop, XOR, ...).
-#  - map        : Map the general logic from NGD file to the components in the
+#                 Map the general logic from NGD file to the components in the
 #                 target FPGA and produces NCD_MAP file.
-#  - par        : PAR stands for Plase & Route. This procedure takes NCD_MAP file,
+#                 PAR stands for Plase & Route. This procedure takes NCD_MAP file,
 #                 places all components and makes routes between them (depending
 #                 on the chosen optimization mode) and produces NCD file.
-#  - implement  : Transfer placed and routed NCD file into the bit file, which can
+#  - bitlife    : Transfer placed and routed NCD file into the bit file, which can
 #                 be then used to configure particular FPGA. When ELF and BMM is
 #                 specified, this procedure fills in location constraints of all
 #                 memories in BMM and initialize them with data from ELF.
 #  - download   : Download bitfile to the target FPGA (by using Impact).
 #  - clean      : Clean build directory, dependency (*.d) files and call
 #                 'make clean' in the directory of ELF file.
-#  - all        : Do 'clean' and 'implement' targets.
+#  - all        : Do 'implement' target.
 
 # Dependicies are handled, so in most cases only 'download' target is called.
 
 
 TOP             = msp_motion
-DEVICE          = xc2v1000-fg456
 
 PRJ             = $(TOP).prj
 UCF             = $(TOP).ucf
@@ -64,10 +59,7 @@ BMM             = memory.bmm
 SW_SRC          = software/$(ARCH)-$(BOARD)-$(APP)
 ELF             = $(SW_SRC)/_compiled/bin/$(APP)
 
-SEARCH_DIRS     = 
-
 JTAG_POS        = 2
-INTSTYLE        = xflow
 
 SRC             = ..
 
@@ -94,12 +86,10 @@ SRCPRJ          = $(addprefix $(SRC),/$(PRJ))
 
 #===============================================================================
 
-.PHONY: all synthesize translate map par implement download download-only clean
-.PHONY: re-synthesize re-translate re-map re-par
-
-implement: $(BITFILE)
+.PHONY: all project synthesize implement bitfile download download-only clean
+.PHONY: re-synthesize
 
-all: clean implement
+all: implement
 
 #===============================================================================
 
@@ -112,43 +102,19 @@ endif
        xtclsh create.tcl $(ISE) $(SRCPRJ)
        xtclsh config.tcl $(ISE)
 
-
 synthesize: $(NGC)
-re-synthesize $(NGC): $(SRCPRJ)
-       echo " \
-         run \
-         $(addprefix -ifn ,$(SRCPRJ)) \
-         -ifmt mixed \
-         -ofn $(TOP).ngc \
-         -ofmt NGC \
-         -top $(TOP) \
-         -p $(DEVICE) \
-         -opt_mode Speed \
-          -keep_hierarchy soft \
-         -opt_level 1" | xst | tee xst.log
-
-
-translate: $(NGD)
-re-translate $(NGD): $(NGC) $(SRC)/$(BMM) $(SRC)/$(UCF)
-ifneq ($(strip $(BMM)),)
-       ln -s -f $(SRC)/$(BMM) $(BMM_LOCAL)
-endif
-       ngdbuild -intstyle $(INTSTYLE) -p $(DEVICE) -uc $(SRC)/$(UCF) \
-         $(addprefix -bm ,$(BMM_LOCAL)) \
-         $(addprefix -sd $(SRC)/,$(SEARCH_DIRS)) \
-         $(NGC) \
-         $(NGD)
-
-map: $(NCD_MAP) $(PCF)
-re-map $(NCD_MAP) $(PCF): $(NGD)
-       map -intstyle $(INTSTYLE) -o $(NCD_MAP) $(NGD) $(PCF)
+re-synthesize $(NGC): $(ISE) $(SRC)/$(UCF) $(BMM_LOCAL)
+       xtclsh process.tcl $(ISE) "Synthesize - XST"
+       @touch $(NGC)
 
-par: $(NCD)
-re-par $(NCD): $(NCD_MAP) $(PCF)
-       par -intstyle $(INTSTYLE) $(NCD_MAP) -w $(NCD) $(PCF)
+implement: $(NCD)
+$(NCD): $(ISE) $(SRC)/$(UCF) $(BMM_LOCAL)
+       xtclsh process.tcl $(ISE) "Implement Design"
+       @touch $(NCD)
 
+bitfile: $(BITFILE)
 $(TOP).bit $(BMM_LOCAL_BD): $(NCD)
-       bitgen -w $(NCD) $(TOP).bit $(PCF)
+       bitgen -ise $(ISE) $(INSTYLE) -w $(NCD) $(TOP).bit $(PCF)
 
 $(TOP)_elf.bit: $(TOP).bit $(BMM_LOCAL_BD) $(SRC)/$(ELF)
        data2mem -bm $(BMM_LOCAL_BD) -bd $(SRC)/$(ELF) -bt $(TOP).bit -o b $(TOP)_elf.bit