Submodule PWM and toplevel updated.

[fpga/virtex2/msp_motion.git] / msp_motion.vhd

diff --git a/msp_motion.vhd b/msp_motion.vhd
index b131d18948e3929c5df9ea173c0b8f34cfc69af4..21ac3e6ec0c26a97abaebd88d164d50090960993 100644 (file)
--- a/msp_motion.vhd
+++ b/msp_motion.vhd
@@ -199,7 +199,7 @@ begin
   ------------------------------------------------------------------------------
   irq (13 downto 1) <= (others => '0');
 
-  motor_irq_ff : process (mclk, puc) is
+  motor_irq_gen : process (mclk, puc) is
   begin
     if rising_edge (mclk) then
       if puc = '1' or irq_acc (0) = '1' then
@@ -247,7 +247,7 @@ begin
 
   -- Motor feedback IRQ generator
   -- f_motor_irq approx. 1 kHz
-  mcc_irq_counter_1 : entity work.counter
+  irq_counter_1 : entity work.counter
     generic map (
       WIDTH => 5,
       MAX   => 22)
@@ -316,9 +316,14 @@ begin
   -- Motion Control Chain
   ------------------------------------------------------------------------------
   mcc_exec_1 : entity work.mcc_exec
+    generic map (
+      AXIS_CNT   => 1,
+      AXIS_CNT_W => 1)
     port map (
       CLK_I      => mclk,
       RST_I      => puc,
+      MCC_AXIS_O => open,
+      MCC_DONE_O => open,
       MCC_EN_I   => '1',
       MCC_EXEC_I => PWM_OW,
       MCC_ERR_O  => open,
@@ -369,7 +374,7 @@ begin
   ------------------------------------------------------------------------------
   -- PWM counter is shared by all PWM generators. Generator contains only
   -- comparator and desired value.
-  counter_1 : entity work.counter
+  pwm_counter : entity work.counter
     generic map (
       WIDTH => PWM_W,
       MAX   => 2**PWM_W - 2)
@@ -387,6 +392,7 @@ begin
       clk     => mclk,
       reset   => puc,
       din     => PWM_DAT,
+      sel     => '1',
       we      => PWM1_STB,
       pwm_cnt => PWM_CNT,
       pwm_cyc => PWM_OW,
@@ -399,6 +405,7 @@ begin
       clk     => mclk,
       reset   => puc,
       din     => PWM_DAT,
+      sel     => '1',
       we      => PWM2_STB,
       pwm_cnt => PWM_CNT,
       pwm_cyc => PWM_OW,
@@ -411,18 +418,20 @@ begin
       clk     => mclk,
       reset   => puc,
       din     => PWM_DAT,
+      sel     => '1',
       we      => PWM3_STB,
       pwm_cnt => PWM_CNT,
       pwm_cyc => PWM_OW,
       pwm     => PWM3_OUT);
 
   -- PWM signals mapped to FPGA outputs, EN forced to '1'
-  PWM0    <= PWM1_OUT;
+  PWM0    <= not PWM1_OUT;
   PWM0_EN <= '1';
-  PWM1    <= PWM2_OUT;
+  PWM1    <= not PWM2_OUT;
   PWM1_EN <= '1';
-  PWM2    <= PWM3_OUT;
+  PWM2    <= not PWM3_OUT;
   PWM2_EN <= '1';
+
   -- PWM is signalized on LEDs
   LED0    <= PWM1_OUT;
   LED1    <= PWM2_OUT;