--- /dev/null
+// ram_generic: 2x16kB, BRAM_TYPE=RAMB16_S2
+ADDRESS_SPACE blockrom RAMB16 [0x8000:0xffff]
+ BUS_BLOCK
+ openMSP430_1/p_ram_lo/BLOCKS[0].RAMB16_S2.B[3].BRAM [7:6];
+ openMSP430_1/p_ram_lo/BLOCKS[0].RAMB16_S2.B[2].BRAM [5:4];
+ openMSP430_1/p_ram_lo/BLOCKS[0].RAMB16_S2.B[1].BRAM [3:2];
+ openMSP430_1/p_ram_lo/BLOCKS[0].RAMB16_S2.B[0].BRAM [1:0];
+ openMSP430_1/p_ram_hi/BLOCKS[0].RAMB16_S2.B[3].BRAM [15:14];
+ openMSP430_1/p_ram_hi/BLOCKS[0].RAMB16_S2.B[2].BRAM [13:12];
+ openMSP430_1/p_ram_hi/BLOCKS[0].RAMB16_S2.B[1].BRAM [11:10];
+ openMSP430_1/p_ram_hi/BLOCKS[0].RAMB16_S2.B[0].BRAM [9:8];
+ END_BUS_BLOCK;
+ BUS_BLOCK
+ openMSP430_1/p_ram_lo/BLOCKS[1].RAMB16_S2.B[3].BRAM [7:6];
+ openMSP430_1/p_ram_lo/BLOCKS[1].RAMB16_S2.B[2].BRAM [5:4];
+ openMSP430_1/p_ram_lo/BLOCKS[1].RAMB16_S2.B[1].BRAM [3:2];
+ openMSP430_1/p_ram_lo/BLOCKS[1].RAMB16_S2.B[0].BRAM [1:0];
+ openMSP430_1/p_ram_hi/BLOCKS[1].RAMB16_S2.B[3].BRAM [15:14];
+ openMSP430_1/p_ram_hi/BLOCKS[1].RAMB16_S2.B[2].BRAM [13:12];
+ openMSP430_1/p_ram_hi/BLOCKS[1].RAMB16_S2.B[1].BRAM [11:10];
+ openMSP430_1/p_ram_hi/BLOCKS[1].RAMB16_S2.B[0].BRAM [9:8];
+ END_BUS_BLOCK;
+END_ADDRESS_SPACE;
+
+
+// ram_generic: 2x4kB, BRAM_TYPE=RAMB_S4
+ADDRESS_SPACE blockram RAMB16 [0x0200:0x21ff]
+ BUS_BLOCK
+ openMSP430_1/d_ram_lo/BLOCKS[0].RAMB16_S4.B[1].BRAM [7:4];
+ openMSP430_1/d_ram_lo/BLOCKS[0].RAMB16_S4.B[0].BRAM [3:0];
+ openMSP430_1/d_ram_hi/BLOCKS[0].RAMB16_S4.B[1].BRAM [15:12];
+ openMSP430_1/d_ram_hi/BLOCKS[0].RAMB16_S4.B[0].BRAM [11:8];
+ END_BUS_BLOCK;
+END_ADDRESS_SPACE;
+
--- /dev/null
+verilog work openmsp430/core/omsp_alu.v
+verilog work openmsp430/core/omsp_clock_module.v
+verilog work openmsp430/core/omsp_dbg.v
+verilog work openmsp430/core/omsp_dbg_hwbrk.v
+verilog work openmsp430/core/omsp_dbg_uart.v
+verilog work openmsp430/core/omsp_execution_unit.v
+verilog work openmsp430/core/omsp_frontend.v
+verilog work openmsp430/core/omsp_mem_backbone.v
+verilog work openmsp430/core/omsp_multiplier.v
+verilog work openmsp430/core/omsp_register_file.v
+verilog work openmsp430/core/omsp_sfr.v
+verilog work openmsp430/core/omsp_watchdog.v
+verilog work openmsp430/core/openMSP430.v
+
+verilog work openmsp430/core/openMSP430_undefines.v
+verilog work openmsp430/core/timescale.v
+
+vhdl work openmsp430/memory/ram_generic.vhd
+
+vhdl work openmsp430/uart/tx_control.vhd
+vhdl work openmsp430/uart/tx.vhd
+vhdl work openmsp430/uart/rx_control.vhd
+vhdl work openmsp430/uart/rx.vhd
+vhdl work openmsp430/uart/fifo.vhd
+vhdl work openmsp430/uart/baud_gen.vhd
+vhdl work openmsp430/uart/uart.vhd
+
+verilog work openmsp430/top/top_8_32_mul/openMSP430_defines.v
+vhdl work openmsp430/top/top_8_32_mul/openMSP430_8_32_mul.vhd
+
+
+vhdl work msp430_cmdproc.vhd
+
--- /dev/null
+#==============================================================================#
+# Clock & Reset #
+#==============================================================================#
+
+NET "CLK_24MHz" LOC = "A11" | PERIOD = 41.7 ns LOW 20.9 ns;
+NET "RESET" LOC = "B6";
+
+#==============================================================================#
+# RS-232 Port #
+#==============================================================================#
+
+NET "TXD" LOC = "A7"; # output from the board (from FPGA)
+NET "RXD" LOC = "B7"; # input to the board (to FPGA)
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+--------------------------------------------------------------------------------
+
+entity msp430_cmdproc is
+ port (
+ -- Clock & reset
+ CLK_24MHz : in std_logic;
+ RESET : in std_logic;
+ -- RS232
+ RXD : in std_logic;
+ TXD : out std_logic);
+end msp430_cmdproc;
+
+--------------------------------------------------------------------------------
+
+architecture rtl of msp430_cmdproc is
+
+--------------------------------------------------------------------------------
+
+begin
+ -- Soft-core MCU
+ openMSP430_1 : entity work.openMSP430_8_32_mul
+ port map (
+ dco_clk => CLK_24MHz,
+ lfxt_clk => '0',
+ reset_n => RESET,
+ rxd => RXD,
+ txd => TXD,
+ per_addr => open,
+ per_din => open,
+ per_dout => (others => '0'),
+ per_wen => open,
+ per_en => open,
+ nmi => '0',
+ irq => (others => '0'),
+ irq_acc => open,
+ aclk_en => open,
+ smclk_en => open,
+ mclk => open,
+ puc => open);
+
+end rtl;
+