1 #==============================================================================#
3 #==============================================================================#
5 NET "CLK_24MHz" LOC = "A11" | PERIOD = 41.7 ns LOW 20.9 ns;
6 NET "RESET" LOC = "B6";
8 #==============================================================================#
10 #==============================================================================#
12 NET "TXD" LOC = "A7"; # output from the board (from FPGA)
13 NET "RXD" LOC = "B7"; # input to the board (to FPGA)