]> rtime.felk.cvut.cz Git - fpga/virtex2/blink.git/commit
+Softcore configuration and memories desctiption.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Sat, 8 Jan 2011 23:34:49 +0000 (00:34 +0100)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Sat, 8 Jan 2011 23:34:49 +0000 (00:34 +0100)
commit3eef3a0edf2fe05c19b19a0b10c3e5f4bb26dcbb
tree71b40bee7f209cfe73411187175219b44e0d90e5
parentc626143b2620e2bbfc6317d726a7298d42d1f966
+Softcore configuration and memories desctiption.

Added modified opneMSP430 configuration file. Softcore configured as 4kB ROM, 1kB RAM, HW multiplier and no debug interface.
Added .bmm file descibing future instances of memories connected to MCU.
memory.bmm [new file with mode: 0644]
openMSP430_defines.v [new file with mode: 0644]