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(parent: 234564d) | patch
+ Top level design master
authorVladimir Burian <buriavl2@fel.cvut.cz>
Sat, 8 Jan 2011 23:46:02 +0000 (00:46 +0100)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Sat, 8 Jan 2011 23:46:02 +0000 (00:46 +0100)
commitaeaed20385938a8d6a66f50331bf63616e17ea70
treec48651057e707a38c19b3e5e1b5a9c648a930828tree | snapshot
parent234564d16d4f9342891f21aaee8af8a190059cd1commit | diff
+ Top level design

Design can be now implemented and downloaded to the target.
Makefile [new file with mode: 0644] blob
openMSP430_fpga.prj [new file with mode: 0644] blob
openMSP430_fpga.ucf [new file with mode: 0644] blob
openMSP430_fpga.vhd [new file with mode: 0644] blob
MSP430 LED blink - test top level design for Virtex 2 V2MB1000 board