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Resets changed from asynchronous to synchronous.
[fpga/uart.git] / tb /
2011-02-04 Vladimir BurianReceiving capability added to the top component. tree | commitdiff
2011-02-04 Vladimir BurianBaud generator ClockEnable added. tree | commitdiff
2011-02-04 Vladimir BurianReceiver control FSM prototype. tree | commitdiff
2011-02-04 Vladimir BurianFirst prototype of receiver shift register. tree | commitdiff
2011-01-22 Vladimir BurianFirst working prototype of HW UART - TX part. tree | commitdiff
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