Resets changed from asynchronous to synchronous.

[fpga/uart.git] / tx.vhd

diff --git a/tx.vhd b/tx.vhd
index ccf9a86e3f6468204607b510df53a7ffbb6cb287..9d777c78219d28a5414ab14841c130d8a9c08413 100644 (file)
--- a/tx.vhd
+++ b/tx.vhd
@@ -32,12 +32,12 @@ end transmitter;
 architecture behavioral of transmitter is
   
   -- Output shift register (containing also start and stop bit).
-  signal tx_shift_reg : std_logic_vector (9 downto 0);
+  signal tx_shift_reg : std_logic_vector (9 downto 0) := "1111111111";
   -- Register parallel to the output shift register where '1' shows the last
   -- bit of the frame ('1' is in the place of stop bit).
-  signal tx_flag      : std_logic_vector (9 downto 0);
+  signal tx_flag      : std_logic_vector (9 downto 0) := "0000000000";
   -- Transmitting of new frame could be started with next clk.
-  signal tx_ready     : std_logic;
+  signal tx_ready     : std_logic := '1';
 
 --------------------------------------------------------------------------------
 
@@ -45,25 +45,27 @@ begin
 
   process (clk, reset)
   begin
-    if (reset = '1') then
-      tx_shift_reg <= "1111111111";
-      tx_flag <= "0000000000";
-      tx_ready <= '1';
+    if (rising_edge(clk)) then
+      if (reset = '1') then
+        tx_shift_reg <= "1111111111";
+        tx_flag <= "0000000000";
+        tx_ready <= '1';
       
-    elsif (rising_edge(clk)) then
-      if (we = '1') then
-        tx_shift_reg <= '1' & data & '0';
-        tx_flag <= "1000000000";
-        tx_ready <= '0';
-        
-      else
-        tx_shift_reg <= '1' & tx_shift_reg(9 downto 1);
-        tx_flag <= '0' & tx_flag(9 downto 1);
-        
-        if (tx_flag(1) = '1') then
-          tx_ready <= '1';
+      else  
+        if (we = '1') then
+          tx_shift_reg <= '1' & data & '0';
+          tx_flag <= "1000000000";
+          tx_ready <= '0';
+          
+        else
+          tx_shift_reg <= '1' & tx_shift_reg(9 downto 1);
+          tx_flag <= '0' & tx_flag(9 downto 1);
+          
+          if (tx_flag(1) = '1') then
+            tx_ready <= '1';
+          end if;
+          
         end if;
-        
       end if;
     end if;
   end process;