Receiving capability added to the top component.

[fpga/uart.git] / tb / tb_uart.vhd

diff --git a/tb/tb_uart.vhd b/tb/tb_uart.vhd
index b4d1f2217b4138e98d1887965f2e82d4047d9976..f35be5e5a0dbc9b2de55346ee789fddb0a22aafe 100644 (file)
--- a/tb/tb_uart.vhd
+++ b/tb/tb_uart.vhd
@@ -11,7 +11,8 @@ architecture testbench of tb_uart is
 
   component uart is
     generic (
-      output_fifo_width : integer
+      output_fifo_width : integer := 2;
+      input_fifo_width  : integer := 2
     );
     port (
       mclk        : in  std_logic;
@@ -20,10 +21,11 @@ architecture testbench of tb_uart is
       per_en      : in  std_logic;
       per_wen     : in  std_logic_vector (1  downto 0);
       puc         : in  std_logic;
-      --per_irq_acc : in  std_logic;
-      --per_irq     : out std_logic;
+      per_irq_acc : in  std_logic;
+      per_irq     : out std_logic;
       per_dout    : out std_logic_vector (15 downto 0);
 
+      rxd         : in  std_logic;
       txd         : out std_logic
     );
   end component;  
@@ -31,8 +33,8 @@ architecture testbench of tb_uart is
   signal clk   : std_logic;
   signal reset : std_logic;
   
-  constant period : time := 1 us;
-  constant offset : time := 2 us;
+  constant period : time := 200 ns;
+  constant offset : time := 2 * period;
 
 
   signal per_addr : std_logic_vector (7  downto 0);
@@ -40,40 +42,54 @@ architecture testbench of tb_uart is
   signal per_en   : std_logic;
   signal per_wen  : std_logic_vector (1  downto 0);
   signal per_dout : std_logic_vector (15 downto 0);
+  signal per_irq  : std_logic;
 
+  signal rxd      : std_logic;
   signal txd      : std_logic;
 
 
-  type test_record is record
-    we : std_logic;
+  type per_test_record is record
+    we   : std_logic;
     word : std_logic;
     data : std_logic_vector (15 downto 0);
     addr : std_logic_vector (15 downto 0);
   end record;
   
-  type test_array is array (positive range <>) of test_record;
+  type per_test_array is array (positive range <>) of per_test_record;
+  type rxd_test_array is array (positive range <>) of std_logic_vector (7 downto 0);
   
-  constant test_vectors : test_array := (
-    ('1','1',X"0002",X"0100"),
-    ('1','0',X"0065",X"0102")
+  constant addr_offset : std_logic_vector (15 downto 0) := X"0100";
+  
+  constant per_test_vectors : per_test_array := (
+    ('1','1',X"0002",X"0000"),
+    ('1','0',X"0065",X"0002")
+  );
+
+  constant rxd_test_vectors : rxd_test_array := (
+    "01000011",
+    "01000100"
   );
 
 --------------------------------------------------------------------------------
 
 begin
   UUT : uart port map (
-    mclk      => clk,
-    per_addr  => per_addr,
-    per_din   => per_din,
-    per_en    => per_en,
-    per_wen   => per_wen,
-    puc       => reset,
-    per_dout  => per_dout,
-
-    txd       => txd
+    mclk        => clk,
+    per_addr    => per_addr,
+    per_din     => per_din,
+    per_en      => per_en,
+    per_wen     => per_wen,
+    puc         => reset,
+    per_irq_acc => '0',
+    per_irq     => per_irq,
+    per_dout    => per_dout,
+    
+    rxd         => rxd,
+    txd         => txd
   );
 
-
+  
+  -- Clock generation
   process
   begin
     clk <= '0';
@@ -87,7 +103,8 @@ begin
     end loop;
   end process;
 
-
+  
+  -- Reset generation
   process
   begin
     reset <= '0';
@@ -98,9 +115,10 @@ begin
     wait;
   end process;
 
-
+  
+  -- Bus communication with UART peripherial (per_test_vector)
   process
-    variable vector : test_record;
+    variable vector : per_test_record;
   begin
     per_addr <= X"00";
     per_din  <= X"0000";
@@ -110,9 +128,10 @@ begin
     wait for 3.1 * period;
 
 
-    for i in test_vectors'range loop
-      vector := test_vectors(i);
-
+    for i in per_test_vectors'range loop
+      vector := per_test_vectors(i);
+      vector.addr := vector.addr + addr_offset;
+      
       per_addr <= vector.addr (8 downto 1);
       per_en <= '1';
     
@@ -140,6 +159,36 @@ begin
 
     wait;
   end process;
+
+
+  -- UART RXD signal generation (rxd_test_vector)
+  process
+    constant baud_period : time := 6 * period;
+    constant extra_wait  : time := 2 * baud_period;  -- waiting between frames
+    variable vector      : std_logic_vector (7 downto 0);
+  begin
+    rxd <= '1';
+
+    wait for 4.1 * period;
+
+    for i in rxd_test_vectors'range loop
+      vector := rxd_test_vectors (i);
+
+      rxd <= '0';
+      wait for baud_period;
+
+      for j in 7 downto 0 loop
+        rxd <= vector (j);
+        wait for baud_period;
+      end loop;
+
+      rxd <= '1';
+      wait for baud_period;
+      wait for extra_wait;
+    end loop;
+
+    wait;      
+  end process;
   
 end testbench;