Early initialization of all relevant signals.

[fpga/uart.git] / rx.vhd

diff --git a/rx.vhd b/rx.vhd
index 11dc9d9d478f5bdd034c0c50275d485706db98cd..db1c13246b2516daa90266fe18bc65ae45661d20 100644 (file)
--- a/rx.vhd
+++ b/rx.vhd
@@ -32,8 +32,8 @@ entity receiver is
     en            : in  std_logic;
     rx            : in  std_logic;
     ready         : out std_logic;
-    bad_start_bit : out std_logic;
-    bad_stop_bit  : out std_logic;
+    bad_start_bit : out std_logic := '0';
+    bad_stop_bit  : out std_logic := '0';
     data          : out std_logic_vector (7 downto 0));
 end entity receiver;
 
@@ -43,8 +43,8 @@ architecture behavioral of receiver is
   
   signal rx_shift_reg : std_logic_vector (9 downto 0);
   signal rx_flag      : std_logic_vector (9 downto 0);
-  signal rx_ready     : std_logic;
-  signal rx_running   : std_logic;
+  signal rx_ready     : std_logic := '1';
+  signal rx_running   : std_logic := '0';
   
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