Resets changed from asynchronous to synchronous.

[fpga/uart.git] / rx_control.vhd

diff --git a/rx_control.vhd b/rx_control.vhd
index 80904fad877aa8be22a985717cf8191dc88c375f..2fb836f8acaade2cd01f09979a385fa1a37120e6 100644 (file)
--- a/rx_control.vhd
+++ b/rx_control.vhd
@@ -31,69 +31,71 @@ begin
 
   process (clk, reset) is
   begin
-    if reset = '1' then
-      state    <= waiting;
-      rx_reset <= '0';
-      rx_en    <= '0';
-      fifo_we  <= '0';
-      clk_en   <= '0';
-
-    elsif clk'event and clk = '1' then
-      case state is
-        when resetting =>
-          state    <= waiting;
-          rx_reset <= '0';
-          rx_en    <= '0';
-          fifo_we  <= '0';
-          clk_en   <= '0';
-
-
-        when waiting =>
-          rx_reset <= '0';
-          rx_en    <= '0';
-          fifo_we  <= '0';
-          clk_en   <= '0';
-
-          if rx = '0' then
-            state  <= next_frame;
-            rx_en  <= '1';
-            clk_en <= '1';
-          end if;
-
-
-        when next_frame =>
-          rx_reset <= '0';
-          rx_en    <= '1';
-          fifo_we  <= '0';
-          clk_en   <= '1';
-
-          if rx_ready = '0' then
-            if bad_start_bit = '1' then
-              state    <= resetting;
-              rx_reset <= '1';
-              rx_en    <= '0';
-              clk_en   <= '0';
-
-            else
-              state <= receiving;
-              rx_en <= '0';
+    if clk'event and clk = '1' then
+      if reset = '1' then
+        state    <= waiting;
+        rx_reset <= '0';
+        rx_en    <= '0';
+        fifo_we  <= '0';
+        clk_en   <= '0';
+
+      else
+        case state is
+          when resetting =>
+            state    <= waiting;
+            rx_reset <= '0';
+            rx_en    <= '0';
+            fifo_we  <= '0';
+            clk_en   <= '0';
+
+
+          when waiting =>
+            rx_reset <= '0';
+            rx_en    <= '0';
+            fifo_we  <= '0';
+            clk_en   <= '0';
+
+            if rx = '0' then
+              state  <= next_frame;
+              rx_en  <= '1';
+              clk_en <= '1';
             end if;
-          end if;
 
 
-        when receiving =>
-          rx_reset <= '0';
-          rx_en    <= '0';
-          fifo_we  <= '0';
-          clk_en   <= '1';
+          when next_frame =>
+            rx_reset <= '0';
+            rx_en    <= '1';
+            fifo_we  <= '0';
+            clk_en   <= '1';
 
-          if rx_ready = '1' then
-            state   <= waiting;
-            fifo_we <= '1';
-            clk_en  <= '0';
-          end if;
+            if rx_ready = '0' then
+              if bad_start_bit = '1' then
+                state    <= resetting;
+                rx_reset <= '1';
+                rx_en    <= '0';
+                clk_en   <= '0';
 
-      end case;
+              else
+                state <= receiving;
+                rx_en <= '0';
+              end if;
+            end if;
+
+
+          when receiving =>
+            rx_reset <= '0';
+            rx_en    <= '0';
+            fifo_we  <= '0';
+            clk_en   <= '1';
+
+            if rx_ready = '1' then
+              state   <= waiting;
+              fifo_we <= '1';
+              clk_en  <= '0';
+            end if;
+
+        end case;
+      end if;
     end if;
   end process;