use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
+--------------------------------------------------------------------------------
+-- Baud generator is an adjustable clock frequency divider. Division factor
+-- is determined by the value present on the input vector named 'scale' and is
+-- equal to:
+-- f_OUT = f_IN / (2 * (1 + 'scale'))
+--
+-- The divided clock signal has a duty cycle of 50%.
+--
+-- The reset input signal is asynchronous. When held active, the output is 0.
+-- When released, the output starts a new period and goes high with the next
+-- rising edge of the input clock signal.
+--
+-- _ _ _ _ _ _ _ _ _ _ _ _
+-- CLK _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
+-- _________
+-- RESET ____________| |__________________________
+-- ___ __ ___ ___ ___
+-- CLK_BAUD _| |___| |____________| |___| |___| |___
+--
+--------------------------------------------------------------------------------
+
entity baud_gen is
+ generic (
+ SCALE_WIDTH : integer := 16
+ );
port (
clk : in std_logic;
reset : in std_logic;
- scale : in std_logic_vector (15 downto 0);
+ scale : in std_logic_vector (SCALE_WIDTH-1 downto 0);
clk_baud : out std_logic
);
end baud_gen;
architecture behavioral of baud_gen is
- signal counter : std_logic_vector (15 downto 0);
+ signal counter : std_logic_vector (SCALE_WIDTH-1 downto 0);
signal clk_baud_s : std_logic;
--------------------------------------------------------------------------------