2 use IEEE.STD_LOGIC_1164.all;
3 use IEEE.STD_LOGIC_ARITH.all;
4 use IEEE.STD_LOGIC_UNSIGNED.all;
6 --------------------------------------------------------------------------------
7 -- This module controls the bias reversal for a single 7-segment display. The
8 -- clk input xor's the segment data to cause the segment biasing to be swapped.
9 -- The cnt signal should be about 20-30 Hz for LCD to function correctly. The
10 -- common signal is also bias reversed at this same frequency.
12 -- Example: A is off and B is on, COM is driven by clk signal.
14 -- A __| |__| |__| |__| |__
16 -- B |__| |__| |__| |__|
18 -- COM __| |__| |__| |__| |__
20 --------------------------------------------------------------------------------
26 data_in : in std_logic_vector (6 downto 0);
27 lcd_seg : out std_logic_vector (6 downto 0);
28 lcd_com : out std_logic;
29 lcd_dp : out std_logic);
32 --------------------------------------------------------------------------------
34 architecture behavioral of lcd_mux is
39 if (clk'event and clk = '1') then
40 lcd_seg(0) <= data_in(0) xor cnt;
41 lcd_seg(1) <= data_in(1) xor cnt;
42 lcd_seg(2) <= data_in(2) xor cnt;
43 lcd_seg(3) <= data_in(3) xor cnt;
44 lcd_seg(4) <= data_in(4) xor cnt;
45 lcd_seg(5) <= data_in(5) xor cnt;
46 lcd_seg(6) <= data_in(6) xor cnt;
48 lcd_dp <= '0' xor cnt;